Simulation Results: rstmgr

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 98.95
  • line
  • 99.51
  • cond
  • 99.17
  • toggle
  • 99.41
  • fsm
  • None
  • branch
  • 99.83
  • assert
  • 97.99
  • group
  • 97.76
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.170s 120.496us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.060s 102.082us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.720s 59.083us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 6.480s 2011.581us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.520s 153.111us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.440s 188.996us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.720s 59.083us 1 1 100.00
rstmgr_csr_aliasing 1.520s 153.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.860s 130.410us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.520s 526.406us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.250s 154.695us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.570s 1455.126us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.570s 1455.126us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.570s 1455.126us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.570s 1455.126us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 38.090s 13191.351us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.980s 80.699us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.610s 452.245us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.610s 452.245us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.060s 102.082us 1 1 100.00
rstmgr_csr_rw 0.720s 59.083us 1 1 100.00
rstmgr_csr_aliasing 1.520s 153.111us 1 1 100.00
rstmgr_same_csr_outstanding 0.980s 114.655us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.060s 102.082us 1 1 100.00
rstmgr_csr_rw 0.720s 59.083us 1 1 100.00
rstmgr_csr_aliasing 1.520s 153.111us 1 1 100.00
rstmgr_same_csr_outstanding 0.980s 114.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 2.570s 932.212us 1 1 100.00
rstmgr_sec_cm 11.680s 8476.316us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.680s 8476.316us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.680s 8476.316us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.570s 932.212us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.110s 187.028us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.510s 2452.642us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.780s 301.493us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.680s 8476.316us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.720s 59.083us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.720s 59.083us 1 1 100.00