| V1 |
|
96.77% |
| V2 |
|
75.00% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rv_dm_smoke | 3.500s | 622.794us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_hw_reset | 1.020s | 202.518us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_rw | 2.340s | 992.515us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_bit_bash | 17.660s | 7271.037us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_aliasing | 1.780s | 394.562us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_hw_reset | 15.220s | 7725.707us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_rw | 2.030s | 1779.960us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_bit_bash | 39.680s | 22183.772us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_aliasing | 171.630s | 164386.443us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 1.170s | 877.332us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_not_supported | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_not_supported | 0.950s | 262.045us | 1 | 1 | 100.00 | |
| cmderr_exception | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_exception | 1.030s | 341.494us | 1 | 1 | 100.00 | |
| mem_tl_access_resuming | 1 | 1 | 100.00 | |||
| rv_dm_mem_tl_access_resuming | 1.030s | 96.886us | 1 | 1 | 100.00 | |
| mem_tl_access_halted | 1 | 1 | 100.00 | |||
| rv_dm_mem_tl_access_halted | 0.970s | 514.978us | 1 | 1 | 100.00 | |
| cmderr_halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_halt_resume | 1.510s | 1142.149us | 1 | 1 | 100.00 | |
| dataaddr_rw_access | 1 | 1 | 100.00 | |||
| rv_dm_dataaddr_rw_access | 1.340s | 175.318us | 1 | 1 | 100.00 | |
| halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_halt_resume_whereto | 1.110s | 254.508us | 1 | 1 | 100.00 | |
| progbuf_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 1.170s | 877.332us | 1 | 1 | 100.00 | |
| abstractcmd_status | 1 | 1 | 100.00 | |||
| rv_dm_abstractcmd_status | 0.880s | 312.387us | 1 | 1 | 100.00 | |
| progbuf_read_write_execute | 1 | 1 | 100.00 | |||
| rv_dm_progbuf_read_write_execute | 1.160s | 273.896us | 1 | 1 | 100.00 | |
| progbuf_exception | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_exception | 1.030s | 341.494us | 1 | 1 | 100.00 | |
| rom_read_access | 1 | 1 | 100.00 | |||
| rv_dm_rom_read_access | 0.970s | 138.109us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_csr_hw_reset | 2.510s | 294.146us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.710s | 249.211us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_csr_bit_bash | 55.170s | 17527.800us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_csr_aliasing | 19.920s | 627.570us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_csr_mem_rw_with_rand_reset | 1.070s | 56.931us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_dm_csr_aliasing | 19.920s | 627.570us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.710s | 249.211us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rv_dm_mem_walk | 0.980s | 29.676us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rv_dm_mem_partial_access | 1.140s | 94.895us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| idcode | 1 | 1 | 100.00 | |||
| rv_dm_smoke | 3.500s | 622.794us | 1 | 1 | 100.00 | |
| jtag_dtm_hard_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_hard_reset | 1.290s | 863.819us | 1 | 1 | 100.00 | |
| jtag_dtm_idle_hint | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_idle_hint | 0.960s | 220.466us | 1 | 1 | 100.00 | |
| jtag_dmi_failed_op | 1 | 1 | 100.00 | |||
| rv_dm_dmi_failed_op | 0.890s | 179.579us | 1 | 1 | 100.00 | |
| jtag_dmi_dm_inactive | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_dm_inactive | 1.070s | 458.938us | 1 | 1 | 100.00 | |
| sba | 0 | 2 | 0.00 | |||
| rv_dm_sba_tl_access | 531.900s | 300000.000us | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 526.590s | 300000.000us | 0 | 1 | 0.00 | |
| bad_sba | 0 | 1 | 0.00 | |||
| rv_dm_bad_sba_tl_access | 277.350s | 300000.000us | 0 | 1 | 0.00 | |
| sba_autoincrement | 0 | 1 | 0.00 | |||
| rv_dm_autoincr_sba_tl_access | 265.200s | 300000.000us | 0 | 1 | 0.00 | |
| jtag_dmi_debug_disabled | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_debug_disabled | 1.160s | 810.465us | 1 | 1 | 100.00 | |
| sba_debug_disabled | 1 | 1 | 100.00 | |||
| rv_dm_sba_debug_disabled | 1.310s | 632.643us | 1 | 1 | 100.00 | |
| ndmreset_req | 1 | 1 | 100.00 | |||
| rv_dm_ndmreset_req | 1.200s | 310.779us | 1 | 1 | 100.00 | |
| hart_unavail | 1 | 1 | 100.00 | |||
| rv_dm_hart_unavail | 1.180s | 80.629us | 1 | 1 | 100.00 | |
| tap_ctrl_transitions | 1 | 2 | 50.00 | |||
| rv_dm_tap_fsm_rand_reset | 0.810s | 44.157us | 0 | 1 | 0.00 | |
| rv_dm_tap_fsm | 11.570s | 5482.114us | 1 | 1 | 100.00 | |
| hartsel_warl | 1 | 1 | 100.00 | |||
| rv_dm_hartsel_warl | 0.860s | 86.471us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| rv_dm_stress_all | 4.540s | 1735.768us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_dm_alert_test | 1.010s | 168.694us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 0.860s | 86.022us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 0.860s | 86.022us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_dm_csr_aliasing | 19.920s | 627.570us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 2.510s | 294.146us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.710s | 249.211us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 5.830s | 1844.419us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_dm_csr_aliasing | 19.920s | 627.570us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 2.510s | 294.146us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.710s | 249.211us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 5.830s | 1844.419us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_dm_tl_intg_err | 8.020s | 996.194us | 1 | 1 | 100.00 | |
| rv_dm_sec_cm | 1.140s | 921.546us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_dm_tl_intg_err | 8.020s | 996.194us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 1.310s | 632.643us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.750s | 174.472us | 1 | 1 | 100.00 | |
| sec_cm_lc_dft_en_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 1.310s | 632.643us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.750s | 174.472us | 1 | 1 | 100.00 | |
| sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 1 | 1 | 100.00 | |||
| rv_dm_smoke | 3.500s | 622.794us | 1 | 1 | 100.00 | |
| sec_cm_dm_en_ctrl_lc_gated | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 1.110s | 90.321us | 1 | 1 | 100.00 | |
| sec_cm_sba_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 1.050s | 296.022us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 1.050s | 296.022us | 1 | 1 | 100.00 | |
| sec_cm_exec_ctrl_mubi | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 1.110s | 90.321us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_stress_all_with_rand_reset | 0.700s | 26.250us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| rv_dm_scanmode | 0.710s | 12.570us | 1 | 1 | 100.00 | |