Simulation Results: spi_device

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.58
  • line
  • 99.11
  • cond
  • 95.98
  • toggle
  • 87.74
  • fsm
  • 89.36
  • branch
  • 98.33
  • assert
  • 94.27
  • group
  • 69.3
Validation stages
V1
100.00%
V2
98.08%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
spi_device_flash_and_tpm 193.000s 33512.260us 2 2 100.00
csr_hw_reset 2 2 100.00
spi_device_csr_hw_reset 1.220s 42.941us 2 2 100.00
csr_rw 2 2 100.00
spi_device_csr_rw 1.130s 183.500us 2 2 100.00
csr_bit_bash 2 2 100.00
spi_device_csr_bit_bash 14.420s 1395.687us 2 2 100.00
csr_aliasing 2 2 100.00
spi_device_csr_aliasing 10.360s 2795.753us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
spi_device_csr_mem_rw_with_rand_reset 1.920s 364.625us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
spi_device_csr_rw 1.130s 183.500us 2 2 100.00
spi_device_csr_aliasing 10.360s 2795.753us 2 2 100.00
mem_walk 2 2 100.00
spi_device_mem_walk 0.710s 36.572us 2 2 100.00
mem_partial_access 2 2 100.00
spi_device_mem_partial_access 1.620s 63.154us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 2 2 100.00
spi_device_csb_read 0.860s 16.220us 2 2 100.00
mem_parity 1 2 50.00
spi_device_mem_parity 0.940s 404.567us 1 2 50.00
mem_cfg 1 2 50.00
spi_device_ram_cfg 0.730s 33.106us 1 2 50.00
tpm_read 2 2 100.00
spi_device_tpm_rw 0.930s 59.914us 2 2 100.00
tpm_write 2 2 100.00
spi_device_tpm_rw 0.930s 59.914us 2 2 100.00
tpm_hw_reg 4 4 100.00
spi_device_tpm_read_hw_reg 12.150s 6545.450us 2 2 100.00
spi_device_tpm_sts_read 0.980s 503.276us 2 2 100.00
tpm_fully_random_case 2 2 100.00
spi_device_tpm_all 29.330s 9204.053us 2 2 100.00
pass_cmd_filtering 4 4 100.00
spi_device_pass_cmd_filtering 11.280s 3210.036us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
pass_addr_translation 4 4 100.00
spi_device_pass_addr_payload_swap 2.880s 328.247us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
pass_payload_translation 4 4 100.00
spi_device_pass_addr_payload_swap 2.880s 328.247us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
cmd_info_slots 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
cmd_read_status 4 4 100.00
spi_device_intercept 6.860s 870.030us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
cmd_read_jedec 4 4 100.00
spi_device_intercept 6.860s 870.030us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
cmd_read_sfdp 4 4 100.00
spi_device_intercept 6.860s 870.030us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
cmd_fast_read 4 4 100.00
spi_device_intercept 6.860s 870.030us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
cmd_read_pipeline 4 4 100.00
spi_device_intercept 6.860s 870.030us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
flash_cmd_upload 2 2 100.00
spi_device_upload 4.880s 369.195us 2 2 100.00
mailbox_command 2 2 100.00
spi_device_mailbox 6.160s 3995.907us 2 2 100.00
mailbox_cross_outside_command 2 2 100.00
spi_device_mailbox 6.160s 3995.907us 2 2 100.00
mailbox_cross_inside_command 2 2 100.00
spi_device_mailbox 6.160s 3995.907us 2 2 100.00
cmd_read_buffer 4 4 100.00
spi_device_flash_mode 25.600s 12161.386us 2 2 100.00
spi_device_read_buffer_direct 5.960s 4793.695us 2 2 100.00
cmd_dummy_cycle 4 4 100.00
spi_device_mailbox 6.160s 3995.907us 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
quad_spi 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
dual_spi 2 2 100.00
spi_device_flash_all 141.850s 51781.431us 2 2 100.00
4b_3b_feature 2 2 100.00
spi_device_cfg_cmd 2.090s 280.771us 2 2 100.00
write_enable_disable 2 2 100.00
spi_device_cfg_cmd 2.090s 280.771us 2 2 100.00
TPM_with_flash_or_passthrough_mode 2 2 100.00
spi_device_flash_and_tpm 193.000s 33512.260us 2 2 100.00
tpm_and_flash_trans_with_min_inactive_time 2 2 100.00
spi_device_flash_and_tpm_min_idle 126.660s 16638.227us 2 2 100.00
stress_all 2 2 100.00
spi_device_stress_all 76.900s 4810.920us 2 2 100.00
alert_test 2 2 100.00
spi_device_alert_test 0.910s 43.492us 2 2 100.00
intr_test 2 2 100.00
spi_device_intr_test 0.720s 50.924us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
spi_device_tl_errors 1.610s 65.024us 2 2 100.00
tl_d_illegal_access 2 2 100.00
spi_device_tl_errors 1.610s 65.024us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
spi_device_csr_hw_reset 1.220s 42.941us 2 2 100.00
spi_device_csr_rw 1.130s 183.500us 2 2 100.00
spi_device_csr_aliasing 10.360s 2795.753us 2 2 100.00
spi_device_same_csr_outstanding 2.120s 45.304us 2 2 100.00
tl_d_partial_access 8 8 100.00
spi_device_csr_hw_reset 1.220s 42.941us 2 2 100.00
spi_device_csr_rw 1.130s 183.500us 2 2 100.00
spi_device_csr_aliasing 10.360s 2795.753us 2 2 100.00
spi_device_same_csr_outstanding 2.120s 45.304us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 4 4 100.00
spi_device_tl_intg_err 12.580s 2410.198us 2 2 100.00
spi_device_sec_cm 1.080s 36.277us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
spi_device_tl_intg_err 12.580s 2410.198us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 2 100.00
spi_device_flash_mode_ignore_cmds 47.300s 22491.230us 2 2 100.00