| V1 |
|
100.00% |
| V2 |
|
83.33% |
| V2S |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_host_smoke | 22.000s | 851.015us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 21.323us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_host_csr_rw | 1.000s | 17.467us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_host_csr_bit_bash | 2.000s | 125.282us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_host_csr_aliasing | 2.000s | 276.339us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_host_csr_mem_rw_with_rand_reset | 2.000s | 54.017us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_host_csr_rw | 1.000s | 17.467us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 276.339us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_host_mem_walk | 1.000s | 27.184us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_host_mem_partial_access | 1.000s | 17.928us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| performance | 1 | 1 | 100.00 | |||
| spi_host_performance | 6.000s | 19.468us | 1 | 1 | 100.00 | |
| error_event_intr | 3 | 3 | 100.00 | |||
| spi_host_overflow_underflow | 4.000s | 203.489us | 1 | 1 | 100.00 | |
| spi_host_error_cmd | 1.000s | 34.552us | 1 | 1 | 100.00 | |
| spi_host_event | 8.000s | 6540.331us | 1 | 1 | 100.00 | |
| clock_rate | 0 | 1 | 0.00 | |||
| spi_host_speed | 293.000s | 200000.000us | 0 | 1 | 0.00 | |
| speed | 0 | 1 | 0.00 | |||
| spi_host_speed | 293.000s | 200000.000us | 0 | 1 | 0.00 | |
| chip_select_timing | 0 | 1 | 0.00 | |||
| spi_host_speed | 293.000s | 200000.000us | 0 | 1 | 0.00 | |
| sw_reset | 1 | 1 | 100.00 | |||
| spi_host_sw_reset | 5.000s | 97.483us | 1 | 1 | 100.00 | |
| passthrough_mode | 1 | 1 | 100.00 | |||
| spi_host_passthrough_mode | 1.000s | 29.240us | 1 | 1 | 100.00 | |
| cpol_cpha | 0 | 1 | 0.00 | |||
| spi_host_speed | 293.000s | 200000.000us | 0 | 1 | 0.00 | |
| full_cycle | 0 | 1 | 0.00 | |||
| spi_host_speed | 293.000s | 200000.000us | 0 | 1 | 0.00 | |
| duplex | 1 | 1 | 100.00 | |||
| spi_host_smoke | 22.000s | 851.015us | 1 | 1 | 100.00 | |
| tx_rx_only | 1 | 1 | 100.00 | |||
| spi_host_smoke | 22.000s | 851.015us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_host_stress_all | 3.000s | 267.179us | 1 | 1 | 100.00 | |
| spien | 1 | 1 | 100.00 | |||
| spi_host_spien | 10.000s | 1967.410us | 1 | 1 | 100.00 | |
| stall | 1 | 1 | 100.00 | |||
| spi_host_status_stall | 39.000s | 4528.117us | 1 | 1 | 100.00 | |
| Idlecsbactive | 1 | 1 | 100.00 | |||
| spi_host_idlecsbactive | 2.000s | 47.502us | 1 | 1 | 100.00 | |
| data_fifo_status | 1 | 1 | 100.00 | |||
| spi_host_overflow_underflow | 4.000s | 203.489us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_host_alert_test | 1.000s | 20.084us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_host_intr_test | 2.000s | 44.532us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_host_tl_errors | 2.000s | 199.747us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_host_tl_errors | 2.000s | 199.747us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 21.323us | 1 | 1 | 100.00 | |
| spi_host_csr_rw | 1.000s | 17.467us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 276.339us | 1 | 1 | 100.00 | |
| spi_host_same_csr_outstanding | 2.000s | 30.497us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 21.323us | 1 | 1 | 100.00 | |
| spi_host_csr_rw | 1.000s | 17.467us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 276.339us | 1 | 1 | 100.00 | |
| spi_host_same_csr_outstanding | 2.000s | 30.497us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_host_sec_cm | 2.000s | 48.123us | 1 | 1 | 100.00 | |
| spi_host_tl_intg_err | 2.000s | 88.363us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_host_tl_intg_err | 2.000s | 88.363us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| spi_host_upper_range_clkdiv | 172.000s | 11023.143us | 1 | 1 | 100.00 | |