Simulation Results: sram_ctrl

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 92.76
  • line
  • 97.96
  • cond
  • 92.17
  • toggle
  • 90.66
  • fsm
  • 80.95
  • branch
  • 95.96
  • assert
  • 95.51
  • group
  • 96.1
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
sram_ctrl_smoke 7.300s 1008.451us 2 2 100.00
csr_hw_reset 2 2 100.00
sram_ctrl_csr_hw_reset 0.710s 33.072us 2 2 100.00
csr_rw 2 2 100.00
sram_ctrl_csr_rw 0.650s 34.100us 2 2 100.00
csr_bit_bash 2 2 100.00
sram_ctrl_csr_bit_bash 1.420s 161.157us 2 2 100.00
csr_aliasing 2 2 100.00
sram_ctrl_csr_aliasing 0.810s 13.612us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.230s 4338.472us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
sram_ctrl_csr_rw 0.650s 34.100us 2 2 100.00
sram_ctrl_csr_aliasing 0.810s 13.612us 2 2 100.00
mem_walk 2 2 100.00
sram_ctrl_mem_walk 218.430s 13980.351us 2 2 100.00
mem_partial_access 2 2 100.00
sram_ctrl_mem_partial_access 108.870s 9565.301us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 2 2 100.00
sram_ctrl_multiple_keys 239.990s 7262.458us 2 2 100.00
stress_pipeline 2 2 100.00
sram_ctrl_stress_pipeline 253.090s 19202.590us 2 2 100.00
bijection 2 2 100.00
sram_ctrl_bijection 1769.400s 132569.633us 2 2 100.00
access_during_key_req 2 2 100.00
sram_ctrl_access_during_key_req 749.070s 86875.601us 2 2 100.00
lc_escalation 2 2 100.00
sram_ctrl_lc_escalation 26.630s 87887.027us 2 2 100.00
executable 2 2 100.00
sram_ctrl_executable 532.750s 7014.564us 2 2 100.00
partial_access 4 4 100.00
sram_ctrl_partial_access 12.380s 599.778us 2 2 100.00
sram_ctrl_partial_access_b2b 223.790s 57651.735us 2 2 100.00
max_throughput 6 6 100.00
sram_ctrl_max_throughput 20.610s 116.553us 2 2 100.00
sram_ctrl_throughput_w_partial_write 54.290s 3132.765us 2 2 100.00
sram_ctrl_throughput_w_readback 17.910s 194.476us 2 2 100.00
regwen 2 2 100.00
sram_ctrl_regwen 682.070s 26920.307us 2 2 100.00
ram_cfg 2 2 100.00
sram_ctrl_ram_cfg 2.230s 2096.922us 2 2 100.00
stress_all 2 2 100.00
sram_ctrl_stress_all 3142.520s 121073.010us 2 2 100.00
alert_test 2 2 100.00
sram_ctrl_alert_test 0.890s 12.985us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
sram_ctrl_tl_errors 2.260s 86.580us 2 2 100.00
tl_d_illegal_access 2 2 100.00
sram_ctrl_tl_errors 2.260s 86.580us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.710s 33.072us 2 2 100.00
sram_ctrl_csr_rw 0.650s 34.100us 2 2 100.00
sram_ctrl_csr_aliasing 0.810s 13.612us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.810s 71.378us 2 2 100.00
tl_d_partial_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.710s 33.072us 2 2 100.00
sram_ctrl_csr_rw 0.650s 34.100us 2 2 100.00
sram_ctrl_csr_aliasing 0.810s 13.612us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.810s 71.378us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.100s 3782.405us 2 2 100.00
tl_intg_err 2 4 50.00
sram_ctrl_sec_cm 0.680s 1.645us 0 2 0.00
sram_ctrl_tl_intg_err 2.490s 1740.708us 2 2 100.00
prim_count_check 0 2 0.00
sram_ctrl_sec_cm 0.680s 1.645us 0 2 0.00
sec_cm_bus_integrity 2 2 100.00
sram_ctrl_tl_intg_err 2.490s 1740.708us 2 2 100.00
sec_cm_ctrl_config_regwen 2 2 100.00
sram_ctrl_regwen 682.070s 26920.307us 2 2 100.00
sec_cm_readback_config_regwen 2 2 100.00
sram_ctrl_regwen 682.070s 26920.307us 2 2 100.00
sec_cm_exec_config_regwen 2 2 100.00
sram_ctrl_csr_rw 0.650s 34.100us 2 2 100.00
sec_cm_exec_config_mubi 2 2 100.00
sram_ctrl_executable 532.750s 7014.564us 2 2 100.00
sec_cm_exec_intersig_mubi 2 2 100.00
sram_ctrl_executable 532.750s 7014.564us 2 2 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
sram_ctrl_executable 532.750s 7014.564us 2 2 100.00
sec_cm_lc_escalate_en_intersig_mubi 2 2 100.00
sram_ctrl_lc_escalation 26.630s 87887.027us 2 2 100.00
sec_cm_prim_ram_ctrl_mubi 2 2 100.00
sram_ctrl_mubi_enc_err 3.610s 675.951us 2 2 100.00
sec_cm_mem_integrity 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.100s 3782.405us 2 2 100.00
sec_cm_mem_readback 2 2 100.00
sram_ctrl_readback_err 4.320s 1347.461us 2 2 100.00
sec_cm_mem_scramble 2 2 100.00
sram_ctrl_smoke 7.300s 1008.451us 2 2 100.00
sec_cm_addr_scramble 2 2 100.00
sram_ctrl_smoke 7.300s 1008.451us 2 2 100.00
sec_cm_instr_bus_lc_gated 2 2 100.00
sram_ctrl_executable 532.750s 7014.564us 2 2 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 2 0.00
sram_ctrl_sec_cm 0.680s 1.645us 0 2 0.00
sec_cm_key_global_esc 2 2 100.00
sram_ctrl_lc_escalation 26.630s 87887.027us 2 2 100.00
sec_cm_key_local_esc 0 2 0.00
sram_ctrl_sec_cm 0.680s 1.645us 0 2 0.00
sec_cm_init_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.680s 1.645us 0 2 0.00
sec_cm_scramble_key_sideload 2 2 100.00
sram_ctrl_smoke 7.300s 1008.451us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.680s 1.645us 0 2 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
sram_ctrl_stress_all_with_rand_reset 112.870s 2157.284us 2 2 100.00