Simulation Results: sysrst_ctrl

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 83.53
  • line
  • 94.05
  • cond
  • 91.66
  • toggle
  • 100.0
  • fsm
  • 55.13
  • branch
  • 95.11
  • assert
  • 84.96
  • group
  • 63.83
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.200s 2126.337us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.890s 2482.312us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.680s 2229.413us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.200s 2530.971us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.910s 6086.972us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.980s 2083.192us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 18.220s 17137.161us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.140s 3305.658us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.410s 2057.330us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.980s 2083.192us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.140s 3305.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 56.840s 223542.057us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 45.310s 42317.217us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 128.470s 69403.911us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 5.290s 3088.056us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.880s 2531.492us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.270s 2025.211us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.420s 3599.276us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.250s 2618.663us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.620s 6086.401us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 57.060s 31628.011us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 9.540s 8578.722us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.180s 2082.644us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.020s 2035.587us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.710s 2038.987us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.710s 2038.987us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.910s 6086.972us 1 1 100.00
sysrst_ctrl_csr_rw 3.980s 2083.192us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.140s 3305.658us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.990s 4687.835us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.910s 6086.972us 1 1 100.00
sysrst_ctrl_csr_rw 3.980s 2083.192us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.140s 3305.658us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.990s 4687.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 22.700s 22296.347us 1 1 100.00
sysrst_ctrl_sec_cm 7.240s 22163.727us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 22.700s 22296.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 3.790s 22140.855us 1 1 100.00