Simulation Results: uart

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 88.27
  • line
  • 99.17
  • cond
  • 95.33
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 97.44
  • assert
  • 97.12
  • group
  • 49.02
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.820s 937.337us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.930s 28.439us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.830s 31.735us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.480s 248.486us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.010s 106.605us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.950s 56.088us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.830s 31.735us 1 1 100.00
uart_csr_aliasing 1.010s 106.605us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 29.390s 24275.795us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.820s 937.337us 1 1 100.00
uart_tx_rx 29.390s 24275.795us 1 1 100.00
parity_error 2 2 100.00
uart_intr 30.660s 23962.160us 1 1 100.00
uart_rx_parity_err 40.620s 31942.207us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 29.390s 24275.795us 1 1 100.00
uart_intr 30.660s 23962.160us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 34.500s 111330.126us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 27.300s 23007.434us 1 1 100.00
fifo_reset 0 1 0.00
uart_fifo_reset 16.270s 55358.225us 0 1 0.00
rx_frame_err 1 1 100.00
uart_intr 30.660s 23962.160us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 30.660s 23962.160us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 30.660s 23962.160us 1 1 100.00
perf 1 1 100.00
uart_perf 120.190s 7026.118us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 7.450s 4094.294us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 7.450s 4094.294us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.950s 13597.943us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 13.040s 30427.261us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.600s 1649.431us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 41.640s 6730.830us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 700.460s 134477.622us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 309.250s 62760.625us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.730s 41.972us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.790s 11.055us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.640s 73.192us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.640s 73.192us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.930s 28.439us 1 1 100.00
uart_csr_rw 0.830s 31.735us 1 1 100.00
uart_csr_aliasing 1.010s 106.605us 1 1 100.00
uart_same_csr_outstanding 0.830s 60.766us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.930s 28.439us 1 1 100.00
uart_csr_rw 0.830s 31.735us 1 1 100.00
uart_csr_aliasing 1.010s 106.605us 1 1 100.00
uart_same_csr_outstanding 0.830s 60.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.810s 688.107us 1 1 100.00
uart_tl_intg_err 1.480s 172.049us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.480s 172.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 23.560s 1750.623us 1 1 100.00