Simulation Results: adc_ctrl

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 88.89
  • line
  • 99.05
  • cond
  • 95.41
  • toggle
  • 100.0
  • fsm
  • 91.89
  • branch
  • 98.64
  • assert
  • 95.95
  • group
  • 41.29
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.410s 5799.512us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.000s 1026.234us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.890s 347.575us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 13.040s 26758.920us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.450s 872.669us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.890s 472.391us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.890s 347.575us 1 1 100.00
adc_ctrl_csr_aliasing 3.450s 872.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 568.880s 324984.351us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 81.530s 169917.352us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 106.880s 326158.121us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 556.450s 329713.051us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 139.510s 349506.774us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 217.580s 399324.165us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 155.020s 180113.815us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 136.390s 2000000.000us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 4.150s 5628.904us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 66.890s 44105.160us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 74.250s 74008.427us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 1518.670s 1765916.234us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.060s 426.691us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.180s 351.642us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.550s 357.301us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.550s 357.301us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.000s 1026.234us 1 1 100.00
adc_ctrl_csr_rw 0.890s 347.575us 1 1 100.00
adc_ctrl_csr_aliasing 3.450s 872.669us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.890s 3727.460us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.000s 1026.234us 1 1 100.00
adc_ctrl_csr_rw 0.890s 347.575us 1 1 100.00
adc_ctrl_csr_aliasing 3.450s 872.669us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.890s 3727.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.320s 8646.990us 1 1 100.00
adc_ctrl_tl_intg_err 9.560s 4488.006us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 9.560s 4488.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 14.270s 37584.123us 1 1 100.00