Simulation Results: edn

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 82.64
  • line
  • 97.57
  • cond
  • 88.28
  • toggle
  • 80.23
  • fsm
  • 48.26
  • branch
  • 91.79
  • assert
  • 96.22
  • group
  • 76.15
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.070s 99.614us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 66.580us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.100s 109.593us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.470s 121.900us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 24.115us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.200s 50.536us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.100s 109.593us 1 1 100.00
edn_csr_aliasing 1.080s 24.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.040s 154.193us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.040s 154.193us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.040s 154.193us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 28.518us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.080s 92.121us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 29.428us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 13.676us 1 1 100.00
edn_disable_auto_req_mode 1.250s 27.336us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.380s 434.002us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 16.085us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.100s 51.428us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.540s 33.383us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.540s 33.383us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 66.580us 1 1 100.00
edn_csr_rw 1.100s 109.593us 1 1 100.00
edn_csr_aliasing 1.080s 24.115us 1 1 100.00
edn_same_csr_outstanding 1.400s 73.647us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 66.580us 1 1 100.00
edn_csr_rw 1.100s 109.593us 1 1 100.00
edn_csr_aliasing 1.080s 24.115us 1 1 100.00
edn_same_csr_outstanding 1.400s 73.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.740s 537.545us 1 1 100.00
edn_tl_intg_err 1.510s 66.026us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.040s 18.740us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.080s 92.121us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.740s 537.545us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.740s 537.545us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.740s 537.545us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.740s 537.545us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.080s 92.121us 1 1 100.00
edn_sec_cm 6.740s 537.545us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.080s 92.121us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.510s 66.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 81.290s 19702.044us 1 1 100.00