Simulation Results: hmac

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.52
  • line
  • 99.74
  • cond
  • 96.01
  • toggle
  • 100.0
  • fsm
  • 91.18
  • branch
  • 99.01
  • assert
  • 96.42
  • group
  • 44.28
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.980s 390.999us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.750s 27.623us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.730s 36.362us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.680s 1094.300us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.560s 390.415us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.060s 118.731us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.730s 36.362us 1 1 100.00
hmac_csr_aliasing 2.560s 390.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 58.120s 21658.309us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 39.710s 998.436us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 215.240s 56900.735us 1 1 100.00
hmac_test_sha384_vectors 20.020s 1851.573us 1 1 100.00
hmac_test_sha512_vectors 366.570s 21931.430us 1 1 100.00
hmac_test_hmac256_vectors 11.700s 1280.560us 1 1 100.00
hmac_test_hmac384_vectors 6.910s 417.955us 1 1 100.00
hmac_test_hmac512_vectors 9.490s 1203.055us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 17.400s 3072.829us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 202.170s 2959.019us 1 1 100.00
error 1 1 100.00
hmac_error 47.210s 4815.352us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 24.210s 5333.951us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.980s 390.999us 1 1 100.00
hmac_long_msg 58.120s 21658.309us 1 1 100.00
hmac_back_pressure 39.710s 998.436us 1 1 100.00
hmac_datapath_stress 202.170s 2959.019us 1 1 100.00
hmac_burst_wr 17.400s 3072.829us 1 1 100.00
hmac_stress_all 57.700s 12755.153us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.980s 390.999us 1 1 100.00
hmac_long_msg 58.120s 21658.309us 1 1 100.00
hmac_back_pressure 39.710s 998.436us 1 1 100.00
hmac_datapath_stress 202.170s 2959.019us 1 1 100.00
hmac_wipe_secret 24.210s 5333.951us 1 1 100.00
hmac_test_sha256_vectors 215.240s 56900.735us 1 1 100.00
hmac_test_sha384_vectors 20.020s 1851.573us 1 1 100.00
hmac_test_sha512_vectors 366.570s 21931.430us 1 1 100.00
hmac_test_hmac256_vectors 11.700s 1280.560us 1 1 100.00
hmac_test_hmac384_vectors 6.910s 417.955us 1 1 100.00
hmac_test_hmac512_vectors 9.490s 1203.055us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.980s 390.999us 1 1 100.00
hmac_long_msg 58.120s 21658.309us 1 1 100.00
hmac_back_pressure 39.710s 998.436us 1 1 100.00
hmac_datapath_stress 202.170s 2959.019us 1 1 100.00
hmac_burst_wr 17.400s 3072.829us 1 1 100.00
hmac_error 47.210s 4815.352us 1 1 100.00
hmac_wipe_secret 24.210s 5333.951us 1 1 100.00
hmac_test_sha256_vectors 215.240s 56900.735us 1 1 100.00
hmac_test_sha384_vectors 20.020s 1851.573us 1 1 100.00
hmac_test_sha512_vectors 366.570s 21931.430us 1 1 100.00
hmac_test_hmac256_vectors 11.700s 1280.560us 1 1 100.00
hmac_test_hmac384_vectors 6.910s 417.955us 1 1 100.00
hmac_test_hmac512_vectors 9.490s 1203.055us 1 1 100.00
hmac_stress_all 57.700s 12755.153us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 57.700s 12755.153us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.580s 105.437us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.780s 19.840us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.440s 72.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.440s 72.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.750s 27.623us 1 1 100.00
hmac_csr_rw 0.730s 36.362us 1 1 100.00
hmac_csr_aliasing 2.560s 390.415us 1 1 100.00
hmac_same_csr_outstanding 1.670s 461.269us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.750s 27.623us 1 1 100.00
hmac_csr_rw 0.730s 36.362us 1 1 100.00
hmac_csr_aliasing 2.560s 390.415us 1 1 100.00
hmac_same_csr_outstanding 1.670s 461.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.900s 40.289us 1 1 100.00
hmac_tl_intg_err 2.290s 245.193us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.290s 245.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.980s 390.999us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.430s 100.082us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 209.700s 16532.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.100s 47.957us 1 1 100.00