Simulation Results: lc_ctrl

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 84.75
  • line
  • 97.08
  • cond
  • 79.17
  • toggle
  • 74.19
  • fsm
  • 67.02
  • branch
  • 93.51
  • assert
  • 93.85
  • group
  • 88.43
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.140s 112.234us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.890s 175.156us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 103.394us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.220s 28.991us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 20.285us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.860s 36.983us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 103.394us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 20.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.270s 396.217us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.440s 245.940us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.050s 21.982us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.030s 53.335us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.780s 3001.558us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_prog_failure 2.030s 53.335us 1 1 100.00
lc_ctrl_errors 7.780s 3001.558us 1 1 100.00
lc_ctrl_security_escalation 6.020s 949.791us 1 1 100.00
lc_ctrl_jtag_state_failure 5.310s 3080.280us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.640s 342.017us 1 1 100.00
lc_ctrl_jtag_errors 15.500s 24087.806us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 5.870s 2279.668us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.920s 1559.133us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.640s 342.017us 1 1 100.00
lc_ctrl_jtag_errors 15.500s 24087.806us 1 1 100.00
lc_ctrl_jtag_access 6.060s 584.765us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.580s 3768.410us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.430s 47.100us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.770s 607.219us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.150s 608.860us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.810s 721.366us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.040s 24.802us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.570s 468.710us 1 1 100.00
lc_ctrl_jtag_alert_test 0.980s 147.729us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.290s 938.462us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.890s 24.371us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 37.060s 4234.360us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.100s 18.633us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.430s 98.057us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.430s 98.057us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 175.156us 1 1 100.00
lc_ctrl_csr_rw 0.920s 103.394us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 20.285us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.110s 45.974us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 175.156us 1 1 100.00
lc_ctrl_csr_rw 0.920s 103.394us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 20.285us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.110s 45.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
lc_ctrl_tl_intg_err 1.370s 246.547us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.370s 246.547us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.440s 245.940us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.980s 16.302us 0 1 0.00
lc_ctrl_sec_cm 5.790s 1657.703us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.020s 949.791us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 4.270s 396.217us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.920s 1559.133us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.710s 344.519us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.710s 344.519us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.600s 2251.264us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.910s 860.917us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.910s 860.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.950s 12.017us 0 1 0.00