Simulation Results: pattgen

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 98.28
  • block
  • 100.0
  • branch
  • 100.0
  • statement
  • 100.0
  • expression
  • 96.82
  • toggle
  • 96.61
  • fsm
  • None
  • assertion
  • 96.95
  • covergroup
  • 89.42
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 135.488us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 85.345us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 23.177us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 171.343us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 16.317us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 80.185us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 23.177us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 132.000s 43800.509us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 15.000s 2308.670us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 20.494us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 6773.000s 5384688.717us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 12.066us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 24.599us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 36.226us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 36.226us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 85.345us 1 1 100.00
pattgen_csr_rw 2.000s 23.177us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.317us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 13.768us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 85.345us 1 1 100.00
pattgen_csr_rw 2.000s 23.177us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.317us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 13.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 36.562us 1 1 100.00
pattgen_tl_intg_err 2.000s 455.798us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 455.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 15.000s 5602.418us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 56.000s 10079.945us 0 1 0.00