Simulation Results: pwrmgr

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.14
  • line
  • 98.92
  • cond
  • 94.48
  • toggle
  • 90.02
  • fsm
  • 94.0
  • branch
  • 95.42
  • assert
  • 96.08
  • group
  • 97.03
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 1.040s 25.226us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.760s 59.053us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.630s 37.165us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.690s 323.596us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.730s 31.859us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.010s 39.107us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.630s 37.165us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 31.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.920s 354.628us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.920s 354.628us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.930s 38.522us 1 1 100.00
pwrmgr_lowpower_invalid 0.740s 98.100us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.790s 16.099us 1 1 100.00
pwrmgr_reset_invalid 0.850s 169.074us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.790s 16.099us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.980s 296.472us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.010s 353.078us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.770s 61.529us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.690s 717.866us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.740s 209.181us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.330s 999.981us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.330s 999.981us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 59.053us 1 1 100.00
pwrmgr_csr_rw 0.630s 37.165us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 31.859us 1 1 100.00
pwrmgr_same_csr_outstanding 1.130s 50.254us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 59.053us 1 1 100.00
pwrmgr_csr_rw 0.630s 37.165us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 31.859us 1 1 100.00
pwrmgr_same_csr_outstanding 1.130s 50.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.600s 9.674us 0 1 0.00
pwrmgr_sec_cm 0.950s 25.547us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.950s 25.547us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.950s 25.547us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.600s 9.674us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.370s 782.463us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.980s 296.472us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.930s 63.763us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.800s 43.357us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.950s 25.547us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.950s 25.547us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.950s 25.547us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.630s 35.536us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.730s 63.543us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.750s 130.101us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 37.165us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 37.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.840s 90.794us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.780s 2045.307us 1 1 100.00