| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
33.33% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 5.520s | 177.911us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 5.560s | 134.786us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_rw | 3.180s | 387.780us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 3.900s | 606.182us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_aliasing | 5.160s | 173.528us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 5.170s | 620.491us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rom_ctrl_csr_rw | 3.180s | 387.780us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 5.160s | 173.528us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rom_ctrl_mem_walk | 3.060s | 362.816us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rom_ctrl_mem_partial_access | 3.170s | 359.946us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 1 | 1 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 4.230s | 1911.221us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| rom_ctrl_stress_all | 16.320s | 751.483us | 1 | 1 | 100.00 | |
| kmac_err_chk | 1 | 1 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 6.890s | 223.901us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rom_ctrl_alert_test | 3.010s | 371.585us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_errors | 6.640s | 303.318us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_errors | 6.640s | 303.318us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 5.560s | 134.786us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_rw | 3.180s | 387.780us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 5.160s | 173.528us | 1 | 1 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 3.290s | 326.771us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 5.560s | 134.786us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_rw | 3.180s | 387.780us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 5.160s | 173.528us | 1 | 1 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 3.290s | 326.771us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 13.740s | 406.796us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| rom_ctrl_tl_intg_err | 22.670s | 691.196us | 1 | 1 | 100.00 | |
| rom_ctrl_sec_cm | 198.730s | 901.688us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 198.730s | 901.688us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 198.730s | 901.688us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| sec_cm_checker_fsm_local_esc | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 198.730s | 901.688us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 198.730s | 901.688us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 5.520s | 177.911us | 1 | 1 | 100.00 | |
| sec_cm_mem_digest | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 5.520s | 177.911us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 5.520s | 177.911us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_intg_err | 22.670s | 691.196us | 1 | 1 | 100.00 | |
| sec_cm_bus_local_esc | 1 | 2 | 50.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| rom_ctrl_kmac_err_chk | 6.890s | 223.901us | 1 | 1 | 100.00 | |
| sec_cm_mux_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| sec_cm_mux_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 13.160s | 1512.353us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_mem_integrity | 1 | 1 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 13.740s | 406.796us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 198.730s | 901.688us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 239.720s | 47195.190us | 1 | 1 | 100.00 | |