Simulation Results: rom_ctrl

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.69
  • line
  • 99.32
  • cond
  • 94.65
  • toggle
  • 99.57
  • fsm
  • 86.67
  • branch
  • 98.18
  • assert
  • 95.49
  • group
  • 95.94
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.410s 556.099us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.380s 1040.241us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 9.810s 1941.848us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.780s 4154.259us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.290s 289.018us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.240s 5179.638us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 9.810s 1941.848us 1 1 100.00
rom_ctrl_csr_aliasing 7.290s 289.018us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.760s 2786.408us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 8.110s 213.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.820s 759.056us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 23.280s 3109.882us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 15.410s 1077.357us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 9.160s 300.295us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.970s 3124.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.970s 3124.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.380s 1040.241us 1 1 100.00
rom_ctrl_csr_rw 9.810s 1941.848us 1 1 100.00
rom_ctrl_csr_aliasing 7.290s 289.018us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.540s 430.072us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.380s 1040.241us 1 1 100.00
rom_ctrl_csr_rw 9.810s 1941.848us 1 1 100.00
rom_ctrl_csr_aliasing 7.290s 289.018us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.540s 430.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 29.070s 5669.517us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_tl_intg_err 98.390s 1763.425us 1 1 100.00
rom_ctrl_sec_cm 473.650s 2152.758us 0 1 0.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 473.650s 2152.758us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 473.650s 2152.758us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 473.650s 2152.758us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 473.650s 2152.758us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.410s 556.099us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.410s 556.099us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.410s 556.099us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 98.390s 1763.425us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
rom_ctrl_kmac_err_chk 15.410s 1077.357us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 113.190s 10698.223us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 29.070s 5669.517us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 473.650s 2152.758us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 80.880s 1506.604us 1 1 100.00