Simulation Results: spi_device

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.81
  • line
  • 99.02
  • cond
  • 96.12
  • toggle
  • 83.54
  • fsm
  • 89.36
  • branch
  • 98.2
  • assert
  • 86.87
  • group
  • 75.6
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 297.370s 49097.922us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.850s 22.679us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.100s 176.992us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 15.900s 1461.021us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.310s 113.673us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.410s 30.190us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.100s 176.992us 1 1 100.00
spi_device_csr_aliasing 5.310s 113.673us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 10.726us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.380s 76.899us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.080s 58.264us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.970s 7.290us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.840s 9.484us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.500s 165.249us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.500s 165.249us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.920s 12.827us 1 1 100.00
spi_device_tpm_sts_read 1.100s 65.193us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 29.760s 9438.574us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.100s 1085.989us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.980s 16659.887us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.980s 16659.887us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.500s 14012.060us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.500s 14012.060us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.500s 14012.060us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.500s 14012.060us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.500s 14012.060us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.930s 1278.073us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 54.990s 15614.267us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 54.990s 15614.267us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 54.990s 15614.267us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 16.600s 3912.341us 1 1 100.00
spi_device_read_buffer_direct 4.080s 933.598us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 54.990s 15614.267us 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 132.150s 32061.533us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.350s 397.738us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.350s 397.738us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 297.370s 49097.922us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 104.950s 10189.730us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 246.610s 171521.080us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.920s 45.034us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.870s 15.077us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.510s 454.448us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.510s 454.448us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.850s 22.679us 1 1 100.00
spi_device_csr_rw 2.100s 176.992us 1 1 100.00
spi_device_csr_aliasing 5.310s 113.673us 1 1 100.00
spi_device_same_csr_outstanding 3.350s 811.814us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.850s 22.679us 1 1 100.00
spi_device_csr_rw 2.100s 176.992us 1 1 100.00
spi_device_csr_aliasing 5.310s 113.673us 1 1 100.00
spi_device_same_csr_outstanding 3.350s 811.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 16.210s 3504.905us 1 1 100.00
spi_device_sec_cm 1.630s 261.754us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 16.210s 3504.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 130.300s 26058.114us 1 1 100.00