Simulation Results: spi_device

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 91.56
  • line
  • 99.13
  • cond
  • 95.92
  • toggle
  • 87.74
  • fsm
  • 89.36
  • branch
  • 98.39
  • assert
  • 94.41
  • group
  • 75.99
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 211.200s 617340.385us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.250s 27.583us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.520s 79.032us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.730s 948.508us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.100s 313.449us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.490s 309.844us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.520s 79.032us 1 1 100.00
spi_device_csr_aliasing 15.100s 313.449us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.760s 13.030us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.750s 46.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 28.161us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.930s 82.532us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.960s 19.568us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.040s 215.207us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.040s 215.207us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.870s 70944.040us 1 1 100.00
spi_device_tpm_sts_read 0.720s 188.519us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 9.490s 3117.741us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.660s 27.834us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.910s 15488.417us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.910s 15488.417us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.150s 1545.774us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.150s 1545.774us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.150s 1545.774us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.150s 1545.774us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.150s 1545.774us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.350s 227.172us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 19.800s 12106.494us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 19.800s 12106.494us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 19.800s 12106.494us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.000s 104.705us 1 1 100.00
spi_device_read_buffer_direct 11.570s 8590.164us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 19.800s 12106.494us 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 8.790s 1914.141us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.920s 41.871us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.920s 41.871us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 211.200s 617340.385us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 55.970s 7311.449us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 282.970s 86104.284us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.030s 85.643us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.910s 14.196us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.420s 284.707us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.420s 284.707us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.250s 27.583us 1 1 100.00
spi_device_csr_rw 1.520s 79.032us 1 1 100.00
spi_device_csr_aliasing 15.100s 313.449us 1 1 100.00
spi_device_same_csr_outstanding 1.650s 28.159us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.250s 27.583us 1 1 100.00
spi_device_csr_rw 1.520s 79.032us 1 1 100.00
spi_device_csr_aliasing 15.100s 313.449us 1 1 100.00
spi_device_same_csr_outstanding 1.650s 28.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 11.300s 2380.116us 1 1 100.00
spi_device_sec_cm 0.970s 256.491us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.300s 2380.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 252.270s 57237.174us 1 1 100.00