Simulation Results: sram_ctrl

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.16
  • line
  • 99.02
  • cond
  • 92.53
  • toggle
  • 90.71
  • fsm
  • 95.24
  • branch
  • 97.28
  • assert
  • 95.83
  • group
  • 95.55
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 13.180s 1430.734us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.810s 53.927us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.010s 55.024us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.700s 156.643us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.850s 38.830us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.580s 3144.416us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.010s 55.024us 1 1 100.00
sram_ctrl_csr_aliasing 0.850s 38.830us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 264.700s 138478.767us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 94.450s 3284.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 647.780s 56283.985us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 218.110s 5272.977us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 2161.250s 634490.151us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 113.830s 17147.081us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 42.920s 11807.170us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 643.380s 181514.574us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 13.810s 1245.317us 1 1 100.00
sram_ctrl_partial_access_b2b 304.450s 17995.417us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 27.550s 785.840us 1 1 100.00
sram_ctrl_throughput_w_partial_write 21.580s 8179.865us 1 1 100.00
sram_ctrl_throughput_w_readback 5.610s 4039.848us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 400.420s 7798.559us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.940s 369.033us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 896.110s 49965.124us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.710s 25.034us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.200s 107.629us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.200s 107.629us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.810s 53.927us 1 1 100.00
sram_ctrl_csr_rw 1.010s 55.024us 1 1 100.00
sram_ctrl_csr_aliasing 0.850s 38.830us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 67.947us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.810s 53.927us 1 1 100.00
sram_ctrl_csr_rw 1.010s 55.024us 1 1 100.00
sram_ctrl_csr_aliasing 0.850s 38.830us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 67.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 32.980s 7123.660us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.760s 4.132us 0 1 0.00
sram_ctrl_tl_intg_err 1.650s 245.481us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.132us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.650s 245.481us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 400.420s 7798.559us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 400.420s 7798.559us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.010s 55.024us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 643.380s 181514.574us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 643.380s 181514.574us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 643.380s 181514.574us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 42.920s 11807.170us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.520s 2848.416us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 32.980s 7123.660us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.980s 1381.115us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 13.180s 1430.734us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 13.180s 1430.734us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 643.380s 181514.574us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.132us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 42.920s 11807.170us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.132us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.132us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 13.180s 1430.734us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.132us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 18.920s 832.315us 1 1 100.00