Simulation Results: sram_ctrl

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.55
  • line
  • 99.07
  • cond
  • 92.41
  • toggle
  • 90.66
  • fsm
  • 100.0
  • branch
  • 97.98
  • assert
  • 95.79
  • group
  • 92.95
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.710s 78.153us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.860s 15.377us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.780s 38.614us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.180s 99.746us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 17.328us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.140s 201.451us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.780s 38.614us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 17.328us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.120s 226.455us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.010s 776.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 722.250s 105610.071us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 168.770s 4803.778us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 17.950s 3013.942us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 755.780s 11092.453us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.240s 2848.847us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 507.820s 6225.194us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.820s 396.804us 1 1 100.00
sram_ctrl_partial_access_b2b 302.040s 5551.660us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 20.810s 267.573us 1 1 100.00
sram_ctrl_throughput_w_partial_write 20.950s 424.828us 1 1 100.00
sram_ctrl_throughput_w_readback 34.020s 237.696us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 702.970s 8637.320us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.010s 79.358us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1176.680s 8432.486us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.710s 15.228us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.770s 75.336us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.770s 75.336us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.860s 15.377us 1 1 100.00
sram_ctrl_csr_rw 0.780s 38.614us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 17.328us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 11.384us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.860s 15.377us 1 1 100.00
sram_ctrl_csr_rw 0.780s 38.614us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 17.328us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 11.384us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.480s 1884.386us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.860s 123.491us 0 1 0.00
sram_ctrl_tl_intg_err 1.400s 106.210us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.860s 123.491us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.400s 106.210us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 702.970s 8637.320us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 702.970s 8637.320us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.780s 38.614us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 507.820s 6225.194us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 507.820s 6225.194us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 507.820s 6225.194us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.240s 2848.847us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.180s 96.789us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.480s 1884.386us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.980s 29.258us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.710s 78.153us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.710s 78.153us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 507.820s 6225.194us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.860s 123.491us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.240s 2848.847us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.860s 123.491us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.860s 123.491us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.710s 78.153us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.860s 123.491us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.690s 659.461us 1 1 100.00