Simulation Results: uart

 
24/11/2025 21:26:03 sha: 7f0e31e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.5
  • line
  • 99.48
  • cond
  • 96.97
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 98.14
  • assert
  • 97.12
  • group
  • 59.75
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.990s 664.066us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 25.544us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 26.453us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.850s 233.726us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.810s 61.724us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.950s 75.075us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 26.453us 1 1 100.00
uart_csr_aliasing 0.810s 61.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 108.360s 115801.501us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.990s 664.066us 1 1 100.00
uart_tx_rx 108.360s 115801.501us 1 1 100.00
parity_error 2 2 100.00
uart_intr 46.340s 60767.484us 1 1 100.00
uart_rx_parity_err 10.540s 31421.541us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 108.360s 115801.501us 1 1 100.00
uart_intr 46.340s 60767.484us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 47.890s 39351.901us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 25.300s 225160.632us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 58.260s 234419.899us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 46.340s 60767.484us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 46.340s 60767.484us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 46.340s 60767.484us 1 1 100.00
perf 1 1 100.00
uart_perf 105.890s 10540.145us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 9.800s 5933.540us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 9.800s 5933.540us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.360s 2551.653us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.400s 2972.705us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 4.010s 1373.813us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 10.510s 6916.701us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 94.650s 31914.294us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 162.280s 321749.302us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.800s 26.609us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.580s 15.126us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.370s 805.300us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.370s 805.300us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 25.544us 1 1 100.00
uart_csr_rw 0.630s 26.453us 1 1 100.00
uart_csr_aliasing 0.810s 61.724us 1 1 100.00
uart_same_csr_outstanding 0.630s 12.223us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 25.544us 1 1 100.00
uart_csr_rw 0.630s 26.453us 1 1 100.00
uart_csr_aliasing 0.810s 61.724us 1 1 100.00
uart_same_csr_outstanding 0.630s 12.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.980s 546.880us 1 1 100.00
uart_tl_intg_err 1.150s 181.161us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.150s 181.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 5.730s 594.626us 0 1 0.00