Simulation Results: adc_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.42 %
  • code
  • 98.14 %
  • assert
  • 95.79 %
  • func
  • 41.34 %
  • line
  • 99.02 %
  • branch
  • 98.58 %
  • cond
  • 95.82 %
  • toggle
  • 100.00 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.280s 6118.181us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.330s 1044.724us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.110s 512.381us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 13.930s 26553.653us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.360s 1024.035us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.920s 392.586us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.110s 512.381us 1 1 100.00
adc_ctrl_csr_aliasing 2.360s 1024.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 44.170s 326571.970us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 546.920s 331081.148us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 817.030s 481997.557us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 235.320s 332938.043us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 41.060s 166476.078us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 160.410s 408018.447us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 70.070s 186560.316us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 448.470s 341613.111us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.860s 3300.273us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 26.000s 25355.718us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 57.940s 122854.688us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 586.780s 395231.192us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.200s 510.630us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.880s 317.368us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.060s 441.561us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.060s 441.561us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.330s 1044.724us 1 1 100.00
adc_ctrl_csr_rw 1.110s 512.381us 1 1 100.00
adc_ctrl_csr_aliasing 2.360s 1024.035us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.100s 4599.929us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.330s 1044.724us 1 1 100.00
adc_ctrl_csr_rw 1.110s 512.381us 1 1 100.00
adc_ctrl_csr_aliasing 2.360s 1024.035us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.100s 4599.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 14.760s 7979.807us 1 1 100.00
adc_ctrl_tl_intg_err 15.150s 8386.519us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 15.150s 8386.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 2.200s 813.458us 1 1 100.00