| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
95.24% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.790s | 19.640us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.740s | 47.166us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.840s | 79.784us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| clkmgr_csr_bit_bash | 3.680s | 878.894us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| clkmgr_csr_aliasing | 0.890s | 19.250us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.980s | 99.624us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| clkmgr_csr_rw | 0.840s | 79.784us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 0.890s | 19.250us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 1 | 1 | 100.00 | |||
| clkmgr_peri | 0.850s | 127.075us | 1 | 1 | 100.00 | |
| trans_enables | 1 | 1 | 100.00 | |||
| clkmgr_trans | 0.780s | 53.217us | 1 | 1 | 100.00 | |
| extclk | 1 | 1 | 100.00 | |||
| clkmgr_extclk | 0.800s | 48.284us | 1 | 1 | 100.00 | |
| clk_status | 1 | 1 | 100.00 | |||
| clkmgr_clk_status | 0.680s | 17.005us | 1 | 1 | 100.00 | |
| jitter | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.790s | 19.640us | 1 | 1 | 100.00 | |
| frequency | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 1.170s | 283.588us | 1 | 1 | 100.00 | |
| frequency_timeout | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 9.400s | 2061.773us | 1 | 1 | 100.00 | |
| frequency_overflow | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 1.170s | 283.588us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| clkmgr_stress_all | 24.390s | 11267.427us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| clkmgr_alert_test | 0.630s | 14.377us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 1.310s | 94.937us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 1.310s | 94.937us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.740s | 47.166us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.840s | 79.784us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 0.890s | 19.250us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 1.050s | 47.208us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.740s | 47.166us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.840s | 79.784us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 0.890s | 19.250us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 1.050s | 47.208us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| clkmgr_sec_cm | 1.650s | 299.992us | 1 | 1 | 100.00 | |
| clkmgr_tl_intg_err | 1.230s | 61.529us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.230s | 128.366us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.230s | 128.366us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.230s | 128.366us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.230s | 128.366us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 1.460s | 203.966us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| clkmgr_tl_intg_err | 1.230s | 61.529us | 1 | 1 | 100.00 | |
| sec_cm_meas_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 1.170s | 283.588us | 1 | 1 | 100.00 | |
| sec_cm_timeout_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 9.400s | 2061.773us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_shadow | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.230s | 128.366us | 1 | 1 | 100.00 | |
| sec_cm_idle_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_idle_intersig_mubi | 0.700s | 20.658us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_ctrl_intersig_mubi | 0.930s | 93.454us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_clk_byp_req_intersig_mubi | 1.020s | 165.524us | 1 | 1 | 100.00 | |
| sec_cm_clk_handshake_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_clk_handshake_intersig_mubi | 0.690s | 6.912us | 0 | 1 | 0.00 | |
| sec_cm_div_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_div_intersig_mubi | 1.190s | 217.315us | 1 | 1 | 100.00 | |
| sec_cm_jitter_config_mubi | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.840s | 79.784us | 1 | 1 | 100.00 | |
| sec_cm_idle_ctr_redun | 1 | 1 | 100.00 | |||
| clkmgr_sec_cm | 1.650s | 299.992us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.840s | 79.784us | 1 | 1 | 100.00 | |
| sec_cm_clk_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.840s | 79.784us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| clkmgr_sec_cm | 1.650s | 299.992us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 1 | 1 | 100.00 | |||
| clkmgr_regwen | 1.710s | 572.261us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_stress_all_with_rand_reset | 20.430s | 1851.158us | 1 | 1 | 100.00 | |