Simulation Results: csrng

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.42 %
  • code
  • 86.09 %
  • assert
  • 91.57 %
  • func
  • 75.60 %
  • block
  • 96.37 %
  • line
  • 97.22 %
  • branch
  • 91.19 %
  • toggle
  • 91.65 %
  • FSM
  • 64.29 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 86.666us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 22.383us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 29.440us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 23.000s 1996.860us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 158.646us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 83.960us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 29.440us 1 1 100.00
csrng_csr_aliasing 4.000s 158.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 162.508us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 20.000s 1684.638us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 20.000s 1684.638us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 443.000s 16696.746us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 14.572us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 53.868us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 40.404us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 40.404us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 22.383us 1 1 100.00
csrng_csr_rw 2.000s 29.440us 1 1 100.00
csrng_csr_aliasing 4.000s 158.646us 1 1 100.00
csrng_same_csr_outstanding 3.000s 80.934us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 22.383us 1 1 100.00
csrng_csr_rw 2.000s 29.440us 1 1 100.00
csrng_csr_aliasing 4.000s 158.646us 1 1 100.00
csrng_same_csr_outstanding 3.000s 80.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 6.000s 160.883us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 29.440us 1 1 100.00
csrng_regwen 2.000s 15.124us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 162.508us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 443.000s 16696.746us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_updrsp_fsm_sparse 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_update_fsm_sparse 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_blk_enc_fsm_sparse 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_outblk_fsm_sparse 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_drbg_upd_ctr_redun 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_drbg_gen_ctr_redun 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 162.508us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 443.000s 16696.746us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 162.508us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 160.883us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
csrng_sec_cm 3.000s 70.057us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 7.000s 304.761us 1 1 100.00
csrng_err 2.000s 24.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 70.000s 1803.551us 1 1 100.00