Simulation Results: edn

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.44 %
  • code
  • 81.80 %
  • assert
  • 95.56 %
  • func
  • 75.95 %
  • line
  • 97.17 %
  • branch
  • 90.76 %
  • cond
  • 86.84 %
  • toggle
  • 85.95 %
  • FSM
  • 48.26 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.910s 18.686us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 49.996us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.880s 51.664us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.460s 174.669us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.500s 70.954us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.740s 63.961us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.880s 51.664us 1 1 100.00
edn_csr_aliasing 1.500s 70.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.230s 50.513us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.230s 50.513us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.230s 50.513us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.080s 21.666us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.050s 90.709us 1 1 100.00
errs 1 1 100.00
edn_err 0.760s 33.127us 1 1 100.00
disable 2 2 100.00
edn_disable 0.860s 11.339us 1 1 100.00
edn_disable_auto_req_mode 1.060s 138.041us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.670s 102.083us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 74.473us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.840s 16.913us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.480s 272.998us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.480s 272.998us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 49.996us 1 1 100.00
edn_csr_rw 0.880s 51.664us 1 1 100.00
edn_csr_aliasing 1.500s 70.954us 1 1 100.00
edn_same_csr_outstanding 1.380s 319.787us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 49.996us 1 1 100.00
edn_csr_rw 0.880s 51.664us 1 1 100.00
edn_csr_aliasing 1.500s 70.954us 1 1 100.00
edn_same_csr_outstanding 1.380s 319.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.210s 1331.987us 1 1 100.00
edn_sec_cm 3.800s 470.726us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.840s 58.975us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.050s 90.709us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.800s 470.726us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.800s 470.726us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.800s 470.726us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.800s 470.726us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.050s 90.709us 1 1 100.00
edn_sec_cm 3.800s 470.726us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.050s 90.709us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.210s 1331.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 54.110s 14021.091us 1 1 100.00