Simulation Results: flash_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 94.01 %
  • assert
  • 96.62 %
  • func
  • 95.79 %
  • line
  • 95.97 %
  • branch
  • 97.12 %
  • cond
  • 93.43 %
  • toggle
  • 97.84 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 23.880s 31.838us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.140s 56.448us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 14.410s 178.638us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.320s 58.855us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 23.110s 1325.662us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 32.680s 2042.390us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 7.970s 1146.573us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.320s 58.855us 1 1 100.00
flash_ctrl_csr_aliasing 32.680s 2042.390us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.130s 54.351us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.270s 22.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.670s 41.404us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 29.950s 51.084us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1359.100s 184296.143us 1 1 100.00
flash_ctrl_hw_rma_reset 537.340s 40124.060us 1 1 100.00
flash_ctrl_lcmgr_intg 5.550s 22.982us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1698.560s 240703.977us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 305.990s 8337.188us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.340s 117.862us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2147.000s 387358.335us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 61.160s 2082.044us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.130s 28.180us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.420s 228.381us 1 1 100.00
flash_ctrl_re_evict 15.920s 326.339us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 60.530s 213.000us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 60.530s 213.000us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 414.290s 29342.336us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.670s 377.845us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 48.500s 39.148us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 397.800s 13087.291us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 388.650s 819.111us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 831.030s 1829.800us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.290s 40.969us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 106.170s 1785.296us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 12.050s 67.466us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.370s 34.633us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 138.440s 417.488us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 24.670s 4963.191us 1 1 100.00
flash_ctrl_otp_reset 54.340s 68.434us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1359.100s 184296.143us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 105.820s 2113.353us 1 1 100.00
flash_ctrl_intr_wr 48.690s 5126.762us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 84.300s 24701.267us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 160.220s 25457.946us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 44.440s 3100.123us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 37.230s 1343.434us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.180s 217.185us 1 1 100.00
flash_ctrl_ro_derr 97.130s 1555.533us 1 1 100.00
flash_ctrl_rw_derr 159.240s 14765.872us 1 1 100.00
flash_ctrl_derr_detect 103.150s 832.741us 1 1 100.00
flash_ctrl_integrity 420.330s 4458.393us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 13.380s 27.070us 1 1 100.00
flash_ctrl_ro_serr 87.190s 1322.833us 1 1 100.00
flash_ctrl_rw_serr 116.640s 1376.152us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 47.710s 1641.307us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 48.130s 2776.863us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 142.330s 5435.311us 1 1 100.00
flash_ctrl_write_word_sweep 6.460s 61.054us 1 1 100.00
flash_ctrl_read_word_sweep 8.550s 97.343us 1 1 100.00
flash_ctrl_ro 77.300s 563.718us 1 1 100.00
flash_ctrl_rw 336.140s 4504.006us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.730s 307.072us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 698.200s 174619.213us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 83.500s 10019.508us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.540s 97.421us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.740s 18.092us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.630s 39.132us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.630s 39.132us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.410s 178.638us 1 1 100.00
flash_ctrl_csr_rw 8.320s 58.855us 1 1 100.00
flash_ctrl_csr_aliasing 32.680s 2042.390us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.190s 567.485us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.410s 178.638us 1 1 100.00
flash_ctrl_csr_rw 8.320s 58.855us 1 1 100.00
flash_ctrl_csr_aliasing 32.680s 2042.390us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.190s 567.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.340s 32.600us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 9.340s 32.600us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.340s 32.600us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 9.340s 32.600us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 27.260s 248.522us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 179.060s 861.892us 1 1 100.00
flash_ctrl_sec_cm 1553.340s 7372.719us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 179.060s 861.892us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 179.060s 861.892us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.790s 455.035us 1 1 100.00
flash_ctrl_wr_intg 7.030s 161.880us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 23.880s 31.838us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 54.340s 68.434us 1 1 100.00
flash_ctrl_disable 12.050s 67.466us 1 1 100.00
flash_ctrl_sec_info_access 43.440s 33744.989us 1 1 100.00
flash_ctrl_connect 7.370s 34.633us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.480s 21.805us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.320s 58.855us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.340s 32.600us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.320s 58.855us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.340s 32.600us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.320s 58.855us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.340s 32.600us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 12.050s 67.466us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.790s 455.035us 1 1 100.00
flash_ctrl_access_after_disable 5.710s 21.645us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.060s 29.074us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 12.050s 67.466us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.670s 377.845us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 336.140s 4504.006us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 116.640s 1376.152us 1 1 100.00
flash_ctrl_rw_derr 159.240s 14765.872us 1 1 100.00
flash_ctrl_integrity 420.330s 4458.393us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1359.100s 184296.143us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.340s 7372.719us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.340s 7372.719us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.340s 7372.719us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1553.340s 7372.719us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.010s 854.172us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.920s 108.579us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 8.630s 24.037us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1553.340s 7372.719us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.340s 7372.719us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.340s 7372.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 16.790s 35.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 277.680s 2917.879us 1 1 100.00