Simulation Results: hmac

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.07 %
  • code
  • 97.73 %
  • assert
  • 96.42 %
  • func
  • 43.05 %
  • line
  • 99.63 %
  • branch
  • 98.84 %
  • cond
  • 96.07 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.130s 27.318us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.810s 26.705us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.850s 58.898us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.780s 15081.281us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.890s 163.854us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.210s 129.625us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.850s 58.898us 1 1 100.00
hmac_csr_aliasing 5.890s 163.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 30.580s 6700.952us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 14.720s 973.306us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.590s 302.352us 1 1 100.00
hmac_test_sha384_vectors 20.540s 986.525us 1 1 100.00
hmac_test_sha512_vectors 345.020s 114583.104us 1 1 100.00
hmac_test_hmac256_vectors 9.890s 1243.554us 1 1 100.00
hmac_test_hmac384_vectors 12.220s 1111.182us 1 1 100.00
hmac_test_hmac512_vectors 9.220s 1015.666us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 20.530s 10814.301us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 25.170s 675.287us 1 1 100.00
error 1 1 100.00
hmac_error 0.710s 17.018us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 7.170s 174.955us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.130s 27.318us 1 1 100.00
hmac_long_msg 30.580s 6700.952us 1 1 100.00
hmac_back_pressure 14.720s 973.306us 1 1 100.00
hmac_datapath_stress 25.170s 675.287us 1 1 100.00
hmac_burst_wr 20.530s 10814.301us 1 1 100.00
hmac_stress_all 147.510s 34362.884us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.130s 27.318us 1 1 100.00
hmac_long_msg 30.580s 6700.952us 1 1 100.00
hmac_back_pressure 14.720s 973.306us 1 1 100.00
hmac_datapath_stress 25.170s 675.287us 1 1 100.00
hmac_wipe_secret 7.170s 174.955us 1 1 100.00
hmac_test_sha256_vectors 7.590s 302.352us 1 1 100.00
hmac_test_sha384_vectors 20.540s 986.525us 1 1 100.00
hmac_test_sha512_vectors 345.020s 114583.104us 1 1 100.00
hmac_test_hmac256_vectors 9.890s 1243.554us 1 1 100.00
hmac_test_hmac384_vectors 12.220s 1111.182us 1 1 100.00
hmac_test_hmac512_vectors 9.220s 1015.666us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.130s 27.318us 1 1 100.00
hmac_long_msg 30.580s 6700.952us 1 1 100.00
hmac_back_pressure 14.720s 973.306us 1 1 100.00
hmac_datapath_stress 25.170s 675.287us 1 1 100.00
hmac_burst_wr 20.530s 10814.301us 1 1 100.00
hmac_error 0.710s 17.018us 1 1 100.00
hmac_wipe_secret 7.170s 174.955us 1 1 100.00
hmac_test_sha256_vectors 7.590s 302.352us 1 1 100.00
hmac_test_sha384_vectors 20.540s 986.525us 1 1 100.00
hmac_test_sha512_vectors 345.020s 114583.104us 1 1 100.00
hmac_test_hmac256_vectors 9.890s 1243.554us 1 1 100.00
hmac_test_hmac384_vectors 12.220s 1111.182us 1 1 100.00
hmac_test_hmac512_vectors 9.220s 1015.666us 1 1 100.00
hmac_stress_all 147.510s 34362.884us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 147.510s 34362.884us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.660s 35.472us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.720s 19.757us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.550s 141.873us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.550s 141.873us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.810s 26.705us 1 1 100.00
hmac_csr_rw 0.850s 58.898us 1 1 100.00
hmac_csr_aliasing 5.890s 163.854us 1 1 100.00
hmac_same_csr_outstanding 1.480s 148.193us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.810s 26.705us 1 1 100.00
hmac_csr_rw 0.850s 58.898us 1 1 100.00
hmac_csr_aliasing 5.890s 163.854us 1 1 100.00
hmac_same_csr_outstanding 1.480s 148.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.950s 74.266us 1 1 100.00
hmac_tl_intg_err 1.720s 1391.211us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.720s 1391.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.130s 27.318us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.540s 629.728us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 28.140s 1971.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.140s 31.077us 1 1 100.00