Simulation Results: lc_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.30 %
  • code
  • 84.82 %
  • assert
  • 94.13 %
  • func
  • 85.94 %
  • line
  • 97.08 %
  • branch
  • 93.97 %
  • cond
  • 79.10 %
  • toggle
  • 80.53 %
  • FSM
  • 73.40 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.660s 80.926us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.780s 45.137us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.740s 59.712us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.940s 338.689us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 26.918us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.050s 92.289us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.740s 59.712us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 26.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.100s 2.502us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.500s 527.222us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.760s 36.941us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.490s 102.255us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.360s 1566.740us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_prog_failure 1.490s 102.255us 1 1 100.00
lc_ctrl_errors 8.360s 1566.740us 1 1 100.00
lc_ctrl_security_escalation 4.940s 1505.351us 1 1 100.00
lc_ctrl_jtag_state_failure 5.020s 265.465us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.730s 183.436us 1 1 100.00
lc_ctrl_jtag_errors 13.460s 1242.848us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.880s 345.634us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.180s 260.045us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.900s 619.155us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.430s 784.979us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.030s 76.912us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.480s 125.303us 1 1 100.00
lc_ctrl_jtag_alert_test 2.100s 197.450us 1 1 100.00
lc_ctrl_jtag_smoke 7.350s 2872.930us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.390s 284.760us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.730s 183.436us 1 1 100.00
lc_ctrl_jtag_errors 13.460s 1242.848us 1 1 100.00
lc_ctrl_jtag_access 1.600s 230.767us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.620s 726.477us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.990s 534.526us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 17.259us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 20.850s 7768.475us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.110s 41.113us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.340s 211.812us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.340s 211.812us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 45.137us 1 1 100.00
lc_ctrl_csr_rw 0.740s 59.712us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 26.918us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 140.534us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 45.137us 1 1 100.00
lc_ctrl_csr_rw 0.740s 59.712us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 26.918us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 140.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.300s 289.843us 1 1 100.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.300s 289.843us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.500s 527.222us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.100s 3.421us 0 1 0.00
lc_ctrl_sec_cm 5.540s 131.309us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.940s 1505.351us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.100s 2.502us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3.390s 284.760us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.560s 254.621us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.560s 254.621us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.990s 1862.731us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.430s 1128.106us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.430s 1128.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.190s 1922.570us 0 1 0.00