Simulation Results: lc_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.03 %
  • code
  • 84.53 %
  • assert
  • 94.13 %
  • func
  • 88.43 %
  • line
  • 97.11 %
  • branch
  • 93.77 %
  • cond
  • 79.35 %
  • toggle
  • 80.83 %
  • FSM
  • 71.58 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.450s 68.949us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.100s 21.945us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.190s 116.427us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.710s 47.511us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 458.255us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.180s 34.202us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.190s 116.427us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 458.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.540s 12.872us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.910s 1053.891us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.960us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.690s 35.097us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.580s 747.490us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_prog_failure 1.690s 35.097us 1 1 100.00
lc_ctrl_errors 5.580s 747.490us 1 1 100.00
lc_ctrl_security_escalation 3.810s 1013.793us 1 1 100.00
lc_ctrl_jtag_state_failure 6.800s 652.823us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.000s 2160.448us 1 1 100.00
lc_ctrl_jtag_errors 26.780s 1407.036us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.200s 48.668us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.750s 52.690us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.580s 543.969us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.760s 621.544us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.170s 52.081us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.620s 85.525us 1 1 100.00
lc_ctrl_jtag_alert_test 1.110s 430.332us 1 1 100.00
lc_ctrl_jtag_smoke 3.040s 970.678us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.550s 2009.072us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 2160.448us 1 1 100.00
lc_ctrl_jtag_errors 26.780s 1407.036us 1 1 100.00
lc_ctrl_jtag_access 6.190s 1646.565us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 24.940s 1867.586us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.220s 633.549us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.850s 24.009us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 18.690s 3169.398us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.980s 32.888us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.490s 54.634us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.490s 54.634us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.100s 21.945us 1 1 100.00
lc_ctrl_csr_rw 1.190s 116.427us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 458.255us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 42.897us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.100s 21.945us 1 1 100.00
lc_ctrl_csr_rw 1.190s 116.427us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 458.255us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 42.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.800s 129.338us 1 1 100.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.800s 129.338us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.910s 1053.891us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.880s 21.973us 0 1 0.00
lc_ctrl_sec_cm 5.970s 755.311us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.810s 1013.793us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 1.540s 12.872us 0 1 0.00
lc_ctrl_jtag_state_post_trans 10.550s 2009.072us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.850s 435.212us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.850s 435.212us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.130s 1374.313us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.230s 161.290us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.230s 161.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.370s 4.555us 0 1 0.00