Simulation Results: pattgen

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.76 %
  • code
  • 97.90 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 93.70 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 48.135us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 46.455us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 48.537us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 4.000s 1087.656us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 46.248us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 23.936us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 48.537us 1 1 100.00
pattgen_csr_aliasing 1.000s 46.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 498.000s 87606.279us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 56.000s 9538.817us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 32.759us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 1.000s 29.794us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 46.732us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 77.340us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 19.734us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 19.734us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 46.455us 1 1 100.00
pattgen_csr_rw 1.000s 48.537us 1 1 100.00
pattgen_csr_aliasing 1.000s 46.248us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 29.784us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 46.455us 1 1 100.00
pattgen_csr_rw 1.000s 48.537us 1 1 100.00
pattgen_csr_aliasing 1.000s 46.248us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 29.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 2.000s 908.137us 1 1 100.00
pattgen_tl_intg_err 2.000s 46.872us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 46.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 26.000s 3576.419us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 3.000s 83.016us 1 1 100.00