Simulation Results: pwrmgr

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.96 %
  • code
  • 94.60 %
  • assert
  • 96.08 %
  • func
  • 97.20 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.63 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.860s 24.550us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.900s 25.881us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.710s 64.956us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.490s 514.356us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.900s 32.438us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.410s 51.087us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.710s 64.956us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 32.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.910s 88.233us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.910s 88.233us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.930s 49.514us 1 1 100.00
pwrmgr_lowpower_invalid 0.960s 53.699us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.810s 55.529us 1 1 100.00
pwrmgr_reset_invalid 0.930s 98.098us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.810s 55.529us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.680s 63.719us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.950s 152.159us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.800s 41.239us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.360s 584.391us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.770s 17.236us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.690s 361.283us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.690s 361.283us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.900s 25.881us 1 1 100.00
pwrmgr_csr_rw 0.710s 64.956us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 32.438us 1 1 100.00
pwrmgr_same_csr_outstanding 0.970s 80.250us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.900s 25.881us 1 1 100.00
pwrmgr_csr_rw 0.710s 64.956us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 32.438us 1 1 100.00
pwrmgr_same_csr_outstanding 0.970s 80.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.860s 7.218us 0 1 0.00
pwrmgr_tl_intg_err 0.710s 10.841us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.860s 7.218us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.860s 7.218us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.710s 10.841us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.870s 1214.979us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.680s 63.719us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.030s 72.906us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.630s 106.187us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.860s 7.218us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.860s 7.218us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.860s 7.218us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.790s 35.528us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.760s 83.025us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.080s 289.980us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.710s 64.956us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.710s 64.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.880s 91.727us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.370s 9263.697us 1 1 100.00