Simulation Results: rom_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.27 %
  • code
  • 97.63 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.32 %
  • branch
  • 98.18 %
  • cond
  • 97.33 %
  • toggle
  • 99.97 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.090s 932.526us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.990s 554.703us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.280s 209.956us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.900s 1600.198us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.750s 130.272us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.740s 1865.989us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.280s 209.956us 1 1 100.00
rom_ctrl_csr_aliasing 3.750s 130.272us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.690s 865.323us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.850s 309.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.320s 576.284us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.120s 434.303us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.850s 312.985us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.540s 316.948us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.900s 1797.687us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.900s 1797.687us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.990s 554.703us 1 1 100.00
rom_ctrl_csr_rw 3.280s 209.956us 1 1 100.00
rom_ctrl_csr_aliasing 3.750s 130.272us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.420s 181.066us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.990s 554.703us 1 1 100.00
rom_ctrl_csr_rw 3.280s 209.956us 1 1 100.00
rom_ctrl_csr_aliasing 3.750s 130.272us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.420s 181.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.730s 1155.150us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 101.850s 1439.694us 1 1 100.00
rom_ctrl_tl_intg_err 25.330s 204.039us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 101.850s 1439.694us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 101.850s 1439.694us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 101.850s 1439.694us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 101.850s 1439.694us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.090s 932.526us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.090s 932.526us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.090s 932.526us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 25.330s 204.039us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
rom_ctrl_kmac_err_chk 7.850s 312.985us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 51.220s 13464.485us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.730s 1155.150us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 101.850s 1439.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 56.480s 24578.612us 1 1 100.00