Simulation Results: rom_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.39 %
  • code
  • 95.23 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 100.00 %
  • FSM
  • 80.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.690s 1161.205us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.760s 212.119us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.000s 538.306us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.820s 295.384us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.530s 295.375us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.350s 312.252us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.000s 538.306us 1 1 100.00
rom_ctrl_csr_aliasing 9.530s 295.375us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.540s 293.117us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.160s 374.130us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.820s 390.336us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.200s 2647.223us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 15.730s 553.535us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.470s 391.218us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.100s 207.080us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.100s 207.080us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.760s 212.119us 1 1 100.00
rom_ctrl_csr_rw 7.000s 538.306us 1 1 100.00
rom_ctrl_csr_aliasing 9.530s 295.375us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.900s 298.087us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.760s 212.119us 1 1 100.00
rom_ctrl_csr_rw 7.000s 538.306us 1 1 100.00
rom_ctrl_csr_aliasing 9.530s 295.375us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.900s 298.087us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.310s 1058.937us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 462.240s 1333.558us 1 1 100.00
rom_ctrl_tl_intg_err 96.680s 1625.324us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 462.240s 1333.558us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 462.240s 1333.558us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 462.240s 1333.558us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 462.240s 1333.558us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.690s 1161.205us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.690s 1161.205us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.690s 1161.205us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 96.680s 1625.324us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
rom_ctrl_kmac_err_chk 15.730s 553.535us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 80.170s 8132.107us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.310s 1058.937us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 462.240s 1333.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 110.610s 5531.891us 1 1 100.00