Simulation Results: rstmgr

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.25 %
  • code
  • 99.39 %
  • assert
  • 97.86 %
  • func
  • 97.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.89 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 0.990s 120.909us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.760s 97.908us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.700s 62.701us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.190s 274.071us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.000s 107.037us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.930s 116.989us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.700s 62.701us 1 1 100.00
rstmgr_csr_aliasing 1.000s 107.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.880s 85.905us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.150s 119.206us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.000s 148.452us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.530s 1703.118us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.530s 1703.118us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.530s 1703.118us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.530s 1703.118us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 19.950s 7783.793us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.670s 67.190us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.960s 396.942us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.960s 396.942us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.760s 97.908us 1 1 100.00
rstmgr_csr_rw 0.700s 62.701us 1 1 100.00
rstmgr_csr_aliasing 1.000s 107.037us 1 1 100.00
rstmgr_same_csr_outstanding 0.890s 86.621us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.760s 97.908us 1 1 100.00
rstmgr_csr_rw 0.700s 62.701us 1 1 100.00
rstmgr_csr_aliasing 1.000s 107.037us 1 1 100.00
rstmgr_same_csr_outstanding 0.890s 86.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 21.660s 16813.031us 1 1 100.00
rstmgr_tl_intg_err 2.330s 908.454us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 21.660s 16813.031us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 21.660s 16813.031us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.330s 908.454us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.950s 179.650us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.150s 2253.128us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.040s 302.035us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 21.660s 16813.031us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.700s 62.701us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.700s 62.701us 1 1 100.00