| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
33.33% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 1 | 1 | 100.00 | |||
| rv_timer_random | 2.760s | 273.851us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.630s | 50.270us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_timer_csr_rw | 0.760s | 12.908us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.500s | 104.015us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 0.860s | 49.711us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 0.970s | 33.455us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_timer_csr_rw | 0.760s | 12.908us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.860s | 49.711us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 1 | 100.00 | |||
| rv_timer_random_reset | 0.800s | 14.427us | 1 | 1 | 100.00 | |
| disabled | 1 | 1 | 100.00 | |||
| rv_timer_disabled | 1.010s | 96.824us | 1 | 1 | 100.00 | |
| cfg_update_on_fly | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 178.650s | 176315.842us | 1 | 1 | 100.00 | |
| no_interrupt_test | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 178.650s | 176315.842us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| rv_timer_stress_all | 4.370s | 7366.285us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_timer_alert_test | 0.810s | 39.973us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| rv_timer_intr_test | 0.780s | 15.484us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 2.160s | 78.450us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 2.160s | 78.450us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.630s | 50.270us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.760s | 12.908us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.860s | 49.711us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.660s | 56.294us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.630s | 50.270us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.760s | 12.908us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.860s | 49.711us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.660s | 56.294us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_timer_sec_cm | 1.030s | 47.220us | 1 | 1 | 100.00 | |
| rv_timer_tl_intg_err | 1.050s | 160.263us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_timer_tl_intg_err | 1.050s | 160.263us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 0 | 1 | 0.00 | |||
| rv_timer_min | 1.440s | 63.251us | 0 | 1 | 0.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 0.890s | 89.315us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_stress_all_with_rand_reset | 20.120s | 3413.209us | 1 | 1 | 100.00 | |