Simulation Results: spi_device

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.30 %
  • code
  • 93.08 %
  • assert
  • 94.30 %
  • func
  • 71.53 %
  • line
  • 99.07 %
  • branch
  • 98.27 %
  • cond
  • 95.35 %
  • toggle
  • 83.36 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 111.890s 51064.249us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.840s 71.200us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.710s 75.718us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.890s 629.438us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.170s 3378.018us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.150s 92.805us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.710s 75.718us 1 1 100.00
spi_device_csr_aliasing 15.170s 3378.018us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.740s 12.303us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.070s 18.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.780s 47.055us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.680s 1.535us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.710s 3.629us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.040s 122.432us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.040s 122.432us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.580s 210.891us 1 1 100.00
spi_device_tpm_sts_read 0.760s 76.423us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 11.080s 14756.499us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 15.980s 8447.048us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.280s 5630.706us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.280s 5630.706us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.050s 208.622us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.050s 208.622us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.050s 208.622us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.050s 208.622us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.050s 208.622us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.440s 1263.750us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 17.510s 9944.796us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 17.510s 9944.796us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 17.510s 9944.796us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 1.890s 128.491us 1 1 100.00
spi_device_read_buffer_direct 6.120s 826.218us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 17.510s 9944.796us 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 96.310s 24201.118us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 14.240s 2936.048us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 14.240s 2936.048us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 111.890s 51064.249us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 55.550s 258270.184us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 69.280s 13191.827us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.730s 22.131us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.800s 31.082us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.730s 356.657us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.730s 356.657us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.840s 71.200us 1 1 100.00
spi_device_csr_rw 1.710s 75.718us 1 1 100.00
spi_device_csr_aliasing 15.170s 3378.018us 1 1 100.00
spi_device_same_csr_outstanding 1.870s 152.319us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.840s 71.200us 1 1 100.00
spi_device_csr_rw 1.710s 75.718us 1 1 100.00
spi_device_csr_aliasing 15.170s 3378.018us 1 1 100.00
spi_device_same_csr_outstanding 1.870s 152.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 8.980s 2495.471us 1 1 100.00
spi_device_sec_cm 1.080s 98.415us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.980s 2495.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 72.570s 71459.510us 1 1 100.00