Simulation Results: spi_device

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.03 %
  • code
  • 94.17 %
  • assert
  • 94.41 %
  • func
  • 72.52 %
  • line
  • 99.16 %
  • branch
  • 98.44 %
  • cond
  • 96.15 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 13.690s 852.775us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.170s 43.765us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.890s 38.984us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 27.380s 5623.220us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.380s 1212.907us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.400s 102.393us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.890s 38.984us 1 1 100.00
spi_device_csr_aliasing 14.380s 1212.907us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.660s 65.101us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.190s 70.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.810s 28.133us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.920s 89.756us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.750s 26.888us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 6.360s 1370.885us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 6.360s 1370.885us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.780s 1552.295us 1 1 100.00
spi_device_tpm_sts_read 0.710s 20.390us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 10.810s 2956.784us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 9.420s 8734.633us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.880s 17671.488us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.880s 17671.488us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.830s 661.416us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.830s 661.416us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.830s 661.416us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.830s 661.416us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.830s 661.416us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 1.940s 38.696us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 3.450s 652.932us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 3.450s 652.932us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 3.450s 652.932us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.040s 579.663us 1 1 100.00
spi_device_read_buffer_direct 2.720s 145.995us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 3.450s 652.932us 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 239.200s 55410.631us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.320s 31.920us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.320s 31.920us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 13.690s 852.775us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 122.480s 21094.490us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 113.390s 12441.566us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.780s 26.448us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.890s 47.573us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.060s 1038.832us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.060s 1038.832us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.170s 43.765us 1 1 100.00
spi_device_csr_rw 1.890s 38.984us 1 1 100.00
spi_device_csr_aliasing 14.380s 1212.907us 1 1 100.00
spi_device_same_csr_outstanding 1.420s 218.189us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.170s 43.765us 1 1 100.00
spi_device_csr_rw 1.890s 38.984us 1 1 100.00
spi_device_csr_aliasing 14.380s 1212.907us 1 1 100.00
spi_device_same_csr_outstanding 1.420s 218.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 8.070s 624.097us 1 1 100.00
spi_device_sec_cm 0.950s 154.246us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.070s 624.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 70.870s 15875.294us 1 1 100.00