Simulation Results: sram_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.54 %
  • code
  • 85.75 %
  • assert
  • 95.55 %
  • func
  • 93.32 %
  • line
  • 96.51 %
  • branch
  • 93.56 %
  • cond
  • 90.82 %
  • toggle
  • 90.71 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 12.350s 4516.930us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.890s 34.710us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.680s 30.990us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.410s 146.905us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 51.303us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.520s 706.844us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.680s 30.990us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 51.303us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 218.660s 5253.012us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 110.340s 4739.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 861.410s 83797.333us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 271.670s 30696.033us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1080.800s 78702.186us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 96.750s 3577.726us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 35.770s 17133.553us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 33.240s 1140.654us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 18.670s 2676.419us 1 1 100.00
sram_ctrl_partial_access_b2b 243.910s 55010.812us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.740s 3488.156us 1 1 100.00
sram_ctrl_throughput_w_partial_write 44.190s 1235.696us 1 1 100.00
sram_ctrl_throughput_w_readback 16.880s 3443.981us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 460.190s 9181.385us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.670s 2249.320us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2787.100s 309906.568us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.980s 15.516us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.020s 101.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.020s 101.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.890s 34.710us 1 1 100.00
sram_ctrl_csr_rw 0.680s 30.990us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 51.303us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.760s 52.962us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.890s 34.710us 1 1 100.00
sram_ctrl_csr_rw 0.680s 30.990us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 51.303us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.760s 52.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 26.400s 7207.910us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.930s 5.605us 0 1 0.00
sram_ctrl_tl_intg_err 2.080s 204.476us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.930s 5.605us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.080s 204.476us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 460.190s 9181.385us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 460.190s 9181.385us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.680s 30.990us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 33.240s 1140.654us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 33.240s 1140.654us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 33.240s 1140.654us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 35.770s 17133.553us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 5.560s 662.913us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 26.400s 7207.910us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.120s 1440.494us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 12.350s 4516.930us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 12.350s 4516.930us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 33.240s 1140.654us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.930s 5.605us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 35.770s 17133.553us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.930s 5.605us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.930s 5.605us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 12.350s 4516.930us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.930s 5.605us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 28.740s 1374.728us 1 1 100.00