Simulation Results: sram_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 95.39 %
  • assert
  • 95.23 %
  • func
  • 96.29 %
  • line
  • 98.79 %
  • branch
  • 96.46 %
  • cond
  • 91.55 %
  • toggle
  • 90.16 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.580s 573.691us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.980s 23.184us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.670s 13.868us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.440s 154.740us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 14.495us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.990s 141.715us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.670s 13.868us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 14.495us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.280s 2264.762us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.240s 313.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 729.010s 4093.187us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 120.240s 1879.107us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 32.000s 9798.386us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 676.510s 48981.134us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 1.830s 452.116us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 903.910s 17854.487us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 8.050s 96.674us 1 1 100.00
sram_ctrl_partial_access_b2b 296.880s 123220.945us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 25.170s 263.437us 1 1 100.00
sram_ctrl_throughput_w_partial_write 27.240s 128.522us 1 1 100.00
sram_ctrl_throughput_w_readback 32.690s 467.131us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 50.080s 1932.858us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.700s 33.053us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2353.020s 36789.556us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.970s 13.186us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.730s 142.902us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.730s 142.902us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.980s 23.184us 1 1 100.00
sram_ctrl_csr_rw 0.670s 13.868us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 14.495us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.770s 45.451us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.980s 23.184us 1 1 100.00
sram_ctrl_csr_rw 0.670s 13.868us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 14.495us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.770s 45.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.240s 3326.251us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.840s 176.037us 1 1 100.00
sram_ctrl_sec_cm 0.910s 3.094us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.910s 3.094us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.840s 176.037us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 50.080s 1932.858us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 50.080s 1932.858us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.670s 13.868us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 903.910s 17854.487us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 903.910s 17854.487us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 903.910s 17854.487us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 1.830s 452.116us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.040s 41.653us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.240s 3326.251us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 0.900s 24.887us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.580s 573.691us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.580s 573.691us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 903.910s 17854.487us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.910s 3.094us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 1.830s 452.116us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.910s 3.094us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.910s 3.094us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.580s 573.691us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.910s 3.094us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 54.070s 1738.069us 1 1 100.00