Simulation Results: sysrst_ctrl

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.68 %
  • code
  • 95.62 %
  • assert
  • 95.50 %
  • func
  • 71.93 %
  • line
  • 98.33 %
  • branch
  • 98.15 %
  • cond
  • 95.74 %
  • toggle
  • 100.00 %
  • FSM
  • 85.90 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.010s 2112.878us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.680s 2477.051us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.530s 2205.474us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.270s 2572.332us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.520s 6059.968us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2115.011us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 38.670s 41233.046us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.830s 3285.601us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.910s 2187.417us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.660s 2115.011us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.830s 3285.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 67.030s 123672.719us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 179.360s 97265.965us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.070s 3274.859us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.680s 3570.999us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.540s 2530.408us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.280s 2120.715us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 8.240s 4350.691us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.840s 2615.411us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.190s 7600.731us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 55.850s 30484.220us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 78.420s 168058.926us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.630s 2043.018us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.230s 2020.772us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.150s 2030.582us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.150s 2030.582us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.520s 6059.968us 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2115.011us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.830s 3285.601us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.920s 4738.059us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.520s 6059.968us 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2115.011us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.830s 3285.601us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.920s 4738.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 38.780s 22015.793us 1 1 100.00
sysrst_ctrl_tl_intg_err 82.510s 42434.212us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 82.510s 42434.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 7.550s 7774.832us 1 1 100.00