Simulation Results: uart

 
25/11/2025 18:38:29 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.47 %
  • code
  • 96.22 %
  • assert
  • 97.12 %
  • func
  • 57.06 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 96.97 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.010s 504.103us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.700s 12.081us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 18.239us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.770s 696.630us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.700s 26.651us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.980s 25.394us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 18.239us 1 1 100.00
uart_csr_aliasing 0.700s 26.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 76.780s 114210.601us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.010s 504.103us 1 1 100.00
uart_tx_rx 76.780s 114210.601us 1 1 100.00
parity_error 2 2 100.00
uart_intr 17.700s 57772.421us 1 1 100.00
uart_rx_parity_err 16.430s 72051.068us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 76.780s 114210.601us 1 1 100.00
uart_intr 17.700s 57772.421us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 51.140s 55901.079us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 17.040s 33681.220us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 85.720s 231758.576us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 17.700s 57772.421us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 17.700s 57772.421us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 17.700s 57772.421us 1 1 100.00
perf 1 1 100.00
uart_perf 115.920s 7960.557us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.140s 9998.308us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.140s 9998.308us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 5.040s 8289.904us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.830s 4762.258us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.430s 2259.768us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 33.780s 5911.413us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 456.630s 173744.133us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 82.490s 238024.091us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.620s 19.988us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 49.582us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.060s 93.315us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.060s 93.315us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.700s 12.081us 1 1 100.00
uart_csr_rw 0.590s 18.239us 1 1 100.00
uart_csr_aliasing 0.700s 26.651us 1 1 100.00
uart_same_csr_outstanding 0.630s 20.801us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.700s 12.081us 1 1 100.00
uart_csr_rw 0.590s 18.239us 1 1 100.00
uart_csr_aliasing 0.700s 26.651us 1 1 100.00
uart_same_csr_outstanding 0.630s 20.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.710s 172.190us 1 1 100.00
uart_tl_intg_err 0.910s 151.485us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.910s 151.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 34.860s 3305.530us 1 1 100.00