Simulation Results: adc_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.28 %
  • code
  • 96.91 %
  • assert
  • 95.46 %
  • func
  • 39.47 %
  • line
  • 99.02 %
  • branch
  • 98.51 %
  • cond
  • 95.12 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 7.580s 5793.267us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.090s 963.327us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.960s 602.092us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 10.550s 39190.950us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.610s 619.286us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.410s 450.007us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.960s 602.092us 1 1 100.00
adc_ctrl_csr_aliasing 1.610s 619.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 15.720s 160278.607us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 270.130s 160758.951us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 254.990s 325991.532us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 542.010s 324583.752us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 39.470s 172535.630us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 673.630s 409992.325us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 170.030s 344529.499us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 150.230s 161498.116us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.450s 4751.832us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 39.680s 43156.922us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 117.420s 68567.022us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 169.780s 174581.337us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.440s 386.743us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.030s 354.805us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.930s 366.791us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.930s 366.791us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.090s 963.327us 1 1 100.00
adc_ctrl_csr_rw 0.960s 602.092us 1 1 100.00
adc_ctrl_csr_aliasing 1.610s 619.286us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.790s 2663.796us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.090s 963.327us 1 1 100.00
adc_ctrl_csr_rw 0.960s 602.092us 1 1 100.00
adc_ctrl_csr_aliasing 1.610s 619.286us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.790s 2663.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.960s 4350.252us 1 1 100.00
adc_ctrl_tl_intg_err 3.350s 4380.159us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.350s 4380.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 7.180s 14432.333us 1 1 100.00