| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| aon_timer_smoke | 0.990s | 632.339us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.790s | 920.052us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aon_timer_csr_rw | 1.210s | 508.202us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 8.380s | 8768.494us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 0.940s | 621.305us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 0.990s | 462.758us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aon_timer_csr_rw | 1.210s | 508.202us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 0.940s | 621.305us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 1.110s | 469.095us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 0.960s | 294.050us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 1 | 1 | 100.00 | |||
| aon_timer_prescaler | 12.680s | 52317.369us | 1 | 1 | 100.00 | |
| jump | 1 | 1 | 100.00 | |||
| aon_timer_jump | 1.230s | 646.259us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aon_timer_stress_all | 1.170s | 1597.245us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aon_timer_alert_test | 0.940s | 428.554us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| aon_timer_intr_test | 1.290s | 503.437us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 2.000s | 481.221us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 2.000s | 481.221us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.790s | 920.052us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 1.210s | 508.202us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 0.940s | 621.305us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 2.460s | 1117.259us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.790s | 920.052us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 1.210s | 508.202us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 0.940s | 621.305us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 2.460s | 1117.259us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| aon_timer_sec_cm | 2.870s | 3973.494us | 1 | 1 | 100.00 | |
| aon_timer_tl_intg_err | 9.070s | 8070.711us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aon_timer_tl_intg_err | 9.070s | 8070.711us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_max_thold | 0.690s | 611.466us | 1 | 1 | 100.00 | |
| min_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_min_thold | 1.310s | 623.229us | 1 | 1 | 100.00 | |
| wkup_count_hi_cdc | 1 | 1 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 6.310s | 3564.683us | 1 | 1 | 100.00 | |
| custom_intr | 1 | 1 | 100.00 | |||
| aon_timer_custom_intr | 0.810s | 563.384us | 1 | 1 | 100.00 | |
| alternating_on_off | 1 | 1 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 3.770s | 4037.337us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 11.360s | 4978.525us | 1 | 1 | 100.00 | |