| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
85.71% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.730s | 17.269us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.710s | 18.607us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.710s | 24.029us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| clkmgr_csr_bit_bash | 2.430s | 143.327us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| clkmgr_csr_aliasing | 1.020s | 45.129us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 1.480s | 124.933us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| clkmgr_csr_rw | 0.710s | 24.029us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.020s | 45.129us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 1 | 1 | 100.00 | |||
| clkmgr_peri | 0.700s | 14.607us | 1 | 1 | 100.00 | |
| trans_enables | 1 | 1 | 100.00 | |||
| clkmgr_trans | 0.740s | 35.926us | 1 | 1 | 100.00 | |
| extclk | 1 | 1 | 100.00 | |||
| clkmgr_extclk | 0.850s | 76.759us | 1 | 1 | 100.00 | |
| clk_status | 1 | 1 | 100.00 | |||
| clkmgr_clk_status | 0.720s | 23.166us | 1 | 1 | 100.00 | |
| jitter | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.730s | 17.269us | 1 | 1 | 100.00 | |
| frequency | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 1.770s | 539.771us | 1 | 1 | 100.00 | |
| frequency_timeout | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 3.260s | 1161.964us | 1 | 1 | 100.00 | |
| frequency_overflow | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 1.770s | 539.771us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| clkmgr_stress_all | 4.780s | 1895.907us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| clkmgr_alert_test | 0.700s | 16.708us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 3.380s | 623.349us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 3.380s | 623.349us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.710s | 18.607us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.710s | 24.029us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.020s | 45.129us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 1.230s | 171.207us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.710s | 18.607us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.710s | 24.029us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.020s | 45.129us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 1.230s | 171.207us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| clkmgr_sec_cm | 0.800s | 16.986us | 0 | 1 | 0.00 | |
| clkmgr_tl_intg_err | 1.410s | 211.700us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.300s | 178.796us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.300s | 178.796us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.300s | 178.796us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.300s | 178.796us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 2.030s | 369.834us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| clkmgr_tl_intg_err | 1.410s | 211.700us | 1 | 1 | 100.00 | |
| sec_cm_meas_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 1.770s | 539.771us | 1 | 1 | 100.00 | |
| sec_cm_timeout_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 3.260s | 1161.964us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_shadow | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.300s | 178.796us | 1 | 1 | 100.00 | |
| sec_cm_idle_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_idle_intersig_mubi | 0.840s | 33.874us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_ctrl_intersig_mubi | 0.770s | 24.416us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_clk_byp_req_intersig_mubi | 0.720s | 18.660us | 1 | 1 | 100.00 | |
| sec_cm_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_clk_handshake_intersig_mubi | 0.650s | 16.026us | 1 | 1 | 100.00 | |
| sec_cm_div_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_div_intersig_mubi | 0.660s | 16.204us | 1 | 1 | 100.00 | |
| sec_cm_jitter_config_mubi | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.710s | 24.029us | 1 | 1 | 100.00 | |
| sec_cm_idle_ctr_redun | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.800s | 16.986us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.710s | 24.029us | 1 | 1 | 100.00 | |
| sec_cm_clk_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.710s | 24.029us | 1 | 1 | 100.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.800s | 16.986us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 1 | 1 | 100.00 | |||
| clkmgr_regwen | 2.330s | 520.170us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_stress_all_with_rand_reset | 43.300s | 9824.409us | 1 | 1 | 100.00 | |