Simulation Results: edn

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.06 %
  • code
  • 81.06 %
  • assert
  • 95.56 %
  • func
  • 75.57 %
  • line
  • 97.45 %
  • branch
  • 91.20 %
  • cond
  • 83.71 %
  • toggle
  • 83.52 %
  • FSM
  • 49.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.920s 23.974us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.150s 46.139us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.980s 12.030us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.550s 480.274us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.350s 39.210us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.030s 48.889us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.980s 12.030us 1 1 100.00
edn_csr_aliasing 1.350s 39.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.220s 43.028us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.220s 43.028us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.220s 43.028us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.940s 20.918us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.020s 26.637us 1 1 100.00
errs 1 1 100.00
edn_err 1.130s 24.313us 1 1 100.00
disable 2 2 100.00
edn_disable 1.120s 33.591us 1 1 100.00
edn_disable_auto_req_mode 1.330s 95.862us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.420s 571.515us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 50.358us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.050s 14.998us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.600s 309.570us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.600s 309.570us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.150s 46.139us 1 1 100.00
edn_csr_rw 0.980s 12.030us 1 1 100.00
edn_csr_aliasing 1.350s 39.210us 1 1 100.00
edn_same_csr_outstanding 1.180s 60.420us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.150s 46.139us 1 1 100.00
edn_csr_rw 0.980s 12.030us 1 1 100.00
edn_csr_aliasing 1.350s 39.210us 1 1 100.00
edn_same_csr_outstanding 1.180s 60.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.790s 340.837us 1 1 100.00
edn_sec_cm 3.420s 933.546us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 21.658us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.020s 26.637us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.420s 933.546us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.420s 933.546us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.420s 933.546us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.420s 933.546us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.020s 26.637us 1 1 100.00
edn_sec_cm 3.420s 933.546us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.020s 26.637us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.790s 340.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00