Simulation Results: flash_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.38 %
  • code
  • 93.90 %
  • assert
  • 96.53 %
  • func
  • 95.70 %
  • line
  • 95.94 %
  • branch
  • 97.17 %
  • cond
  • 93.74 %
  • toggle
  • 97.64 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
98.46%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 23.250s 126.594us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.530s 28.889us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 10.560s 33.968us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.770s 316.753us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 32.060s 6861.043us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 35.400s 4075.648us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 7.800s 48.568us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.770s 316.753us 1 1 100.00
flash_ctrl_csr_aliasing 35.400s 4075.648us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.480s 28.479us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 8.050s 32.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.790s 23.224us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 19.100s 31.633us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1798.860s 549213.498us 1 1 100.00
flash_ctrl_hw_rma_reset 592.460s 50129.170us 1 1 100.00
flash_ctrl_lcmgr_intg 7.050s 23.850us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1527.030s 333227.975us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 98.850s 96.933us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 10.160s 162.885us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1796.740s 330574.371us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 65.180s 2815.492us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 12.460s 51.237us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.240s 71.509us 1 1 100.00
flash_ctrl_re_evict 15.320s 113.808us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 113.940s 106.176us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 113.940s 106.176us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 573.680s 23352.162us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 13.400s 121.596us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 205.490s 107.186us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 439.460s 3568.847us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 303.390s 864.673us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 693.760s 1533.777us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.850s 59.861us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 122.220s 4889.863us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 12.260s 20.622us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 12.020s 52.852us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 644.010s 457.954us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 19.350s 1457.151us 1 1 100.00
flash_ctrl_otp_reset 51.420s 38.304us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1798.860s 549213.498us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 125.050s 12556.126us 1 1 100.00
flash_ctrl_intr_wr 0.000s 0.000us 0 1 0.00
flash_ctrl_intr_rd_slow_flash 77.390s 5842.039us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 163.370s 97679.525us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 58.500s 893.880us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.810s 701.123us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.330s 49.266us 1 1 100.00
flash_ctrl_ro_derr 76.830s 877.328us 1 1 100.00
flash_ctrl_rw_derr 148.100s 12583.641us 1 1 100.00
flash_ctrl_derr_detect 109.680s 3123.241us 1 1 100.00
flash_ctrl_integrity 402.030s 16592.713us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 14.010s 87.375us 1 1 100.00
flash_ctrl_ro_serr 82.740s 2927.822us 1 1 100.00
flash_ctrl_rw_serr 121.810s 4028.557us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 59.370s 2008.442us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 45.020s 2040.020us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 152.250s 9804.411us 1 1 100.00
flash_ctrl_write_word_sweep 7.130s 403.558us 1 1 100.00
flash_ctrl_read_word_sweep 9.630s 117.936us 1 1 100.00
flash_ctrl_ro 80.050s 5256.195us 1 1 100.00
flash_ctrl_rw 301.500s 3961.896us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.420s 647.179us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 590.700s 40538.802us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 54.990s 10034.945us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.700s 57.444us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.520s 32.266us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.280s 136.533us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.280s 136.533us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 10.560s 33.968us 1 1 100.00
flash_ctrl_csr_rw 9.770s 316.753us 1 1 100.00
flash_ctrl_csr_aliasing 35.400s 4075.648us 1 1 100.00
flash_ctrl_same_csr_outstanding 6.490s 38.749us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 10.560s 33.968us 1 1 100.00
flash_ctrl_csr_rw 9.770s 316.753us 1 1 100.00
flash_ctrl_csr_aliasing 35.400s 4075.648us 1 1 100.00
flash_ctrl_same_csr_outstanding 6.490s 38.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.990s 60.237us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 22.990s 60.237us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.990s 60.237us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 22.990s 60.237us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 9.680s 309.926us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 365.690s 688.387us 1 1 100.00
flash_ctrl_sec_cm 1508.140s 2370.612us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 365.690s 688.387us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 365.690s 688.387us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.690s 210.289us 1 1 100.00
flash_ctrl_wr_intg 7.310s 50.987us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 23.250s 126.594us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 51.420s 38.304us 1 1 100.00
flash_ctrl_disable 12.260s 20.622us 1 1 100.00
flash_ctrl_sec_info_access 44.820s 9343.995us 1 1 100.00
flash_ctrl_connect 12.020s 52.852us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.920s 22.216us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.770s 316.753us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.990s 60.237us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.770s 316.753us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.990s 60.237us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.770s 316.753us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.990s 60.237us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 12.260s 20.622us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.690s 210.289us 1 1 100.00
flash_ctrl_access_after_disable 8.520s 30.418us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.380s 27.455us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 12.260s 20.622us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 13.400s 121.596us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 301.500s 3961.896us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 121.810s 4028.557us 1 1 100.00
flash_ctrl_rw_derr 148.100s 12583.641us 1 1 100.00
flash_ctrl_integrity 402.030s 16592.713us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1798.860s 549213.498us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1508.140s 2370.612us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1508.140s 2370.612us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1508.140s 2370.612us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1508.140s 2370.612us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.150s 822.153us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.170s 23.949us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.630s 22.843us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1508.140s 2370.612us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1508.140s 2370.612us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1508.140s 2370.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.780s 60.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 109.410s 2133.357us 1 1 100.00