Simulation Results: hmac

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.66 %
  • code
  • 97.10 %
  • assert
  • 96.42 %
  • func
  • 42.46 %
  • line
  • 99.68 %
  • branch
  • 98.84 %
  • cond
  • 95.78 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.460s 3194.159us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.820s 85.872us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.670s 18.463us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.210s 309.878us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.540s 161.991us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 740.790s 432393.039us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.670s 18.463us 1 1 100.00
hmac_csr_aliasing 2.540s 161.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 44.650s 13416.242us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 35.250s 852.011us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.350s 178.428us 1 1 100.00
hmac_test_sha384_vectors 435.610s 15105.618us 1 1 100.00
hmac_test_sha512_vectors 343.750s 99649.484us 1 1 100.00
hmac_test_hmac256_vectors 8.470s 1095.132us 1 1 100.00
hmac_test_hmac384_vectors 9.270s 1358.146us 1 1 100.00
hmac_test_hmac512_vectors 10.850s 700.865us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 0.750s 49.936us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 189.200s 2988.130us 1 1 100.00
error 1 1 100.00
hmac_error 18.180s 980.409us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 79.250s 7510.290us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.460s 3194.159us 1 1 100.00
hmac_long_msg 44.650s 13416.242us 1 1 100.00
hmac_back_pressure 35.250s 852.011us 1 1 100.00
hmac_datapath_stress 189.200s 2988.130us 1 1 100.00
hmac_burst_wr 0.750s 49.936us 1 1 100.00
hmac_stress_all 692.290s 95440.974us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.460s 3194.159us 1 1 100.00
hmac_long_msg 44.650s 13416.242us 1 1 100.00
hmac_back_pressure 35.250s 852.011us 1 1 100.00
hmac_datapath_stress 189.200s 2988.130us 1 1 100.00
hmac_wipe_secret 79.250s 7510.290us 1 1 100.00
hmac_test_sha256_vectors 8.350s 178.428us 1 1 100.00
hmac_test_sha384_vectors 435.610s 15105.618us 1 1 100.00
hmac_test_sha512_vectors 343.750s 99649.484us 1 1 100.00
hmac_test_hmac256_vectors 8.470s 1095.132us 1 1 100.00
hmac_test_hmac384_vectors 9.270s 1358.146us 1 1 100.00
hmac_test_hmac512_vectors 10.850s 700.865us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.460s 3194.159us 1 1 100.00
hmac_long_msg 44.650s 13416.242us 1 1 100.00
hmac_back_pressure 35.250s 852.011us 1 1 100.00
hmac_datapath_stress 189.200s 2988.130us 1 1 100.00
hmac_burst_wr 0.750s 49.936us 1 1 100.00
hmac_error 18.180s 980.409us 1 1 100.00
hmac_wipe_secret 79.250s 7510.290us 1 1 100.00
hmac_test_sha256_vectors 8.350s 178.428us 1 1 100.00
hmac_test_sha384_vectors 435.610s 15105.618us 1 1 100.00
hmac_test_sha512_vectors 343.750s 99649.484us 1 1 100.00
hmac_test_hmac256_vectors 8.470s 1095.132us 1 1 100.00
hmac_test_hmac384_vectors 9.270s 1358.146us 1 1 100.00
hmac_test_hmac512_vectors 10.850s 700.865us 1 1 100.00
hmac_stress_all 692.290s 95440.974us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 692.290s 95440.974us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 83.119us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.700s 23.294us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.250s 234.284us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.250s 234.284us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.820s 85.872us 1 1 100.00
hmac_csr_rw 0.670s 18.463us 1 1 100.00
hmac_csr_aliasing 2.540s 161.991us 1 1 100.00
hmac_same_csr_outstanding 1.290s 113.652us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.820s 85.872us 1 1 100.00
hmac_csr_rw 0.670s 18.463us 1 1 100.00
hmac_csr_aliasing 2.540s 161.991us 1 1 100.00
hmac_same_csr_outstanding 1.290s 113.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.110s 327.695us 1 1 100.00
hmac_tl_intg_err 3.090s 429.479us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.090s 429.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.460s 3194.159us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.090s 505.338us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 58.640s 10657.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.710s 82.790us 1 1 100.00