Simulation Results: lc_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.28 %
  • code
  • 84.21 %
  • assert
  • 94.13 %
  • func
  • 89.50 %
  • line
  • 97.08 %
  • branch
  • 93.82 %
  • cond
  • 79.52 %
  • toggle
  • 81.49 %
  • FSM
  • 69.15 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.700s 953.647us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 37.552us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.800s 24.990us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.420s 267.478us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 41.037us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.890s 27.794us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.800s 24.990us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 41.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.880s 121.649us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.590s 1043.703us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.050s 12.945us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.390s 25.299us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.940s 1615.555us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_prog_failure 1.390s 25.299us 1 1 100.00
lc_ctrl_errors 5.940s 1615.555us 1 1 100.00
lc_ctrl_security_escalation 4.740s 567.212us 1 1 100.00
lc_ctrl_jtag_state_failure 3.800s 219.359us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.670s 524.773us 1 1 100.00
lc_ctrl_jtag_errors 25.490s 15842.274us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.820s 1586.881us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.500s 453.148us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.670s 524.773us 1 1 100.00
lc_ctrl_jtag_errors 25.490s 15842.274us 1 1 100.00
lc_ctrl_jtag_access 2.210s 150.548us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.740s 3023.018us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.250s 87.237us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.070s 127.167us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.560s 413.442us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.480s 361.784us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.980s 134.296us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.260s 523.957us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 180.111us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.250s 1480.612us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 142.678us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 1.650s 38.036us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.860s 49.048us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.710s 93.271us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.710s 93.271us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 37.552us 1 1 100.00
lc_ctrl_csr_rw 0.800s 24.990us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 41.037us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.410s 38.292us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 37.552us 1 1 100.00
lc_ctrl_csr_rw 0.800s 24.990us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 41.037us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.410s 38.292us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
lc_ctrl_tl_intg_err 2.010s 1455.713us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.010s 1455.713us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.590s 1043.703us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.920s 50.355us 0 1 0.00
lc_ctrl_sec_cm 6.530s 239.518us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.740s 567.212us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.880s 121.649us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.500s 453.148us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.230s 573.014us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.230s 573.014us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.310s 811.478us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.810s 274.589us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.810s 274.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 26.870s 1531.494us 0 1 0.00