Simulation Results: lc_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.32 %
  • code
  • 84.69 %
  • assert
  • 94.13 %
  • func
  • 89.15 %
  • line
  • 97.06 %
  • branch
  • 93.77 %
  • cond
  • 79.14 %
  • toggle
  • 80.86 %
  • FSM
  • 72.63 %
Validation stages
V1
100.00%
V2
82.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.880s 55.833us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.990s 25.477us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 36.656us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.010s 47.880us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 67.236us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.910s 43.550us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 36.656us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 67.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3.370s 508.951us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.830s 400.425us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.840s 15.103us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.040s 219.006us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 1.330s 26.656us 0 1 0.00
security_escalation 4 7 57.14
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_prog_failure 2.040s 219.006us 1 1 100.00
lc_ctrl_errors 1.330s 26.656us 0 1 0.00
lc_ctrl_security_escalation 8.970s 430.074us 1 1 100.00
lc_ctrl_jtag_state_failure 2.200s 65.641us 0 1 0.00
lc_ctrl_jtag_prog_failure 5.190s 504.656us 1 1 100.00
lc_ctrl_jtag_errors 77.330s 17417.493us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.040s 861.371us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.780s 1148.848us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.190s 504.656us 1 1 100.00
lc_ctrl_jtag_errors 77.330s 17417.493us 1 1 100.00
lc_ctrl_jtag_access 6.600s 3855.049us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.670s 6354.805us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.090s 172.814us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.550s 37.632us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.630s 945.084us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 14.760s 990.042us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.630s 47.110us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.110s 312.296us 1 1 100.00
lc_ctrl_jtag_alert_test 1.100s 91.944us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.930s 416.657us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.730s 14.664us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 3.990s 125.213us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.060s 75.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.950s 285.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.950s 285.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.990s 25.477us 1 1 100.00
lc_ctrl_csr_rw 0.820s 36.656us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 67.236us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.880s 217.246us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.990s 25.477us 1 1 100.00
lc_ctrl_csr_rw 0.820s 36.656us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 67.236us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.880s 217.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
lc_ctrl_tl_intg_err 1.880s 127.183us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.880s 127.183us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.830s 400.425us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.160s 5.635us 0 1 0.00
lc_ctrl_sec_cm 7.650s 1469.429us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.970s 430.074us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.370s 508.951us 0 1 0.00
lc_ctrl_jtag_state_post_trans 11.780s 1148.848us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.130s 836.796us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.130s 836.796us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.330s 3157.580us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.550s 726.856us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.550s 726.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 5.050s 989.654us 0 1 0.00