Simulation Results: pattgen

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.86 %
  • code
  • 98.22 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 94.67 %
Validation stages
V1
100.00%
V2
87.50%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 14.000s 186.932us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 18.867us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 31.522us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 377.793us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 29.448us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 21.405us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 31.522us 1 1 100.00
pattgen_csr_aliasing 1.000s 29.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 1222.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 18.000s 3528.139us 1 1 100.00
error 1 1 100.00
pattgen_error 12.000s 164.120us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 8.000s 442.325us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 4.000s 15.564us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 31.962us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 103.735us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 103.735us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 18.867us 1 1 100.00
pattgen_csr_rw 1.000s 31.522us 1 1 100.00
pattgen_csr_aliasing 1.000s 29.448us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 138.876us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 18.867us 1 1 100.00
pattgen_csr_rw 1.000s 31.522us 1 1 100.00
pattgen_csr_aliasing 1.000s 29.448us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 138.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 11.000s 334.077us 1 1 100.00
pattgen_tl_intg_err 1.000s 53.909us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 53.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 18.000s 4633.268us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 12.000s 46.234us 1 1 100.00