Simulation Results: rom_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.01 %
  • code
  • 96.74 %
  • assert
  • 95.34 %
  • func
  • 95.94 %
  • line
  • 99.32 %
  • branch
  • 97.81 %
  • cond
  • 93.76 %
  • toggle
  • 99.49 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.220s 501.247us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.290s 181.668us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.160s 127.214us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.990s 539.631us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.030s 1009.520us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.580s 146.701us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.160s 127.214us 1 1 100.00
rom_ctrl_csr_aliasing 5.030s 1009.520us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.520s 206.157us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.110s 385.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.720s 1803.164us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.280s 475.558us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.180s 1435.353us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.610s 132.899us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.210s 125.054us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.210s 125.054us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.290s 181.668us 1 1 100.00
rom_ctrl_csr_rw 5.160s 127.214us 1 1 100.00
rom_ctrl_csr_aliasing 5.030s 1009.520us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.910s 530.683us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.290s 181.668us 1 1 100.00
rom_ctrl_csr_rw 5.160s 127.214us 1 1 100.00
rom_ctrl_csr_aliasing 5.030s 1009.520us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.910s 530.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.140s 1050.007us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 139.070s 1648.741us 0 1 0.00
rom_ctrl_tl_intg_err 42.600s 1103.165us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 139.070s 1648.741us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 139.070s 1648.741us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 139.070s 1648.741us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 139.070s 1648.741us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.220s 501.247us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.220s 501.247us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.220s 501.247us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.600s 1103.165us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
rom_ctrl_kmac_err_chk 6.180s 1435.353us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 60.030s 6664.137us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.140s 1050.007us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 139.070s 1648.741us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 148.640s 1892.725us 1 1 100.00